tag:blogger.com,1999:blog-23248196890283209962024-03-05T19:50:36.632-08:00Going Vertical - The 4D Chips BlogThe era of increasing functionality by expanding die area is over. Much like boundary constrained urban areas, the only option is to Go Vertical. 4D Chips focuses on the community, technical challenges and business issues associated with building stacked die products. <center><strong><a title="4D Chips Company website" href="http://www.4dchips.com">4D Chips site</a></strong></center>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.comBlogger31125tag:blogger.com,1999:blog-2324819689028320996.post-33110144031028374702011-04-04T14:33:00.000-07:002011-04-04T14:34:13.267-07:00Another One Bites the Dust: National SemiAccording to a story in the Wall Street Journal, <a href="http://www.ti.com/" title="Texas Instruments' site" target="_blank">TI</a> plans to acquire <a href="http://www.national.com/analog" title="National Semiconductor's soon to be former site" target="_blank">National Semiconductor</a> for US$6.5B<br />
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<blockquote>Texas Instruments said it will buy National Semiconductor for about $6.5 billion in cash, combining two analog semiconductor companies and continuing a trend of acquisitions in the industry.</blockquote><br />
I guess that <strong>someone</strong> has a lot of cash to throw around. Seriously, though, it's a bit sad to see National Semi being swallowed up. Anyway, here's the <a href="http://newscenter.ti.com/Blogs/newsroom/archive/2011/04/04/ti-to-acquire-national-semiconductor-664670.aspx" title="TI Press Release about National Semi Acquistion" target="_blank">press release</a> from TI. Not that it matters, but I was at a meeting down by the <a href="http://www.google.com/maps?f=q&source=s_q&hl=en&geocode=&q=2900+Semiconductor+Drive,+Santa+Clara,+CA+95052&aq=&sll=37.0625,-95.677068&sspn=52.505328,78.310547&ie=UTF8&hq=&hnear=2900+Semiconductor+Dr,+Santa+Clara,+California+95051&z=17" title="Map of National Semi's HQ" target="_blank">National Semiconductor HQ</a>, this morning, and I had kind thoughts as I drove past.<br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-61469373982649291422011-04-04T08:43:00.000-07:002011-04-04T08:43:08.205-07:00EETimes: Momentum builds for 3-D chipsThe wise folks over at <a href="http://www.eetimes.com/" title="EETimes site" target="_blank">EETimes</a> have a nice <a href="http://www.eetimes.com/electronics-news/4214701/Momentum-builds-for-3-D-chips#" title="EETimes: Momentum builds for 3-D chips" target="_blank">piece</a> identifying the "rise" (get it?) of die stacking.<a name='more'></a><br />
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I agree completely with this bit:<br />
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<blockquote>…There are fears that IC scaling is becoming too costly for most chip makers-or will end in the distant future. <br />
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So instead of scaling, there is another concept on the table: stack and connect devices in a 3-D configuration…</blockquote><br />
My only slight quibble is with the exclusive focus on TSVs. While Through Silicon Vias are clearly the mainstream solution, they still present numerous issues with alignment, die area, thermal expansion and capacitance. I'm still looking for a better way, perhaps something more along the lines of the work going on over at <a href="http://www.monolithic3d.com" title="MonolithIC 3D site" target="_blank">MonolithIC 3D</a>. Anyway, it's nice to see our space <a href="http://www.eetimes.com/electronics-news/4214701/Momentum-builds-for-3-D-chips#" title="EETimes: Momentum builds for 3-D chips" target="_blank">getting some love</a> from EETimes.<br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-5742640152940137542011-03-29T17:13:00.000-07:002011-03-29T17:13:03.304-07:00Wow, Tabula Scores Some Serious $$Congratulations to the folks at <a href="http://www.tabula.com/index.php" title="Tabula homepage" target="_blank">Tabula</a> on raising US$108M in their Series D round. It looks like they'll have an opportunity to take a run at grabbing the brass ring.<br />
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Although, as <a href="http://4dchips.blogspot.com/2010/03/tier-logic-uncloaks-its-3d-fpga-company.html" title="Going Vertical: Tier Logic Uncloaks" target="_blank">mentioned previously</a>, Tabula's third dimension is time, not stacking additional die in Z, the announcement is still really interesting for those of us with scars from the perilous world of start-up FPGA companies (extra points for anyone that remembers eXtensil…).<br />
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Anyway, back to Tabula, <a href="http://www.eetimes.com/" title="EETimes site" target="_blank">EETimes</a> had a <a href="http://www.eetimes.com/223100910" title="EETimes: 3-D architecture promises new type of PLD" target="_blank">nice article</a> describing the company and its technology. The short version is that they enable on-the-fly reprogramming which should allow for better resource usage and performance relative to traditional FPGAs. Of course, we talked about similar approaches at both eXtensil and 4D Chips, but talk is cheap and execution wins every time, so hats off to the team at <a href="http://www.tabula.com/index.php" title="Tabula homepage" target="_blank">Tabula</a>.<br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-67730857586663754202010-08-26T16:55:00.000-07:002010-08-26T17:05:57.994-07:00Is it Packaging, or is it Fab?There's an interesting story up on <a href="http://www.edn.com/" title="EDN site" target="_blank">EDN</a>, titled "<a href="http://www.edn.com/article/510248-Wafer_level_packaging_pushes_past_new_mobile_demands.php" title="EDN: Wafer-level packaging pushes past new mobile demands" target="_blank">Wafer-level packaging pushes past new mobile demands</a>." The gist of the discussion seems to be exploring where packaging ends and 3-D IC fabrication begins.<a name='more'></a> <br />
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This is an especially interesting topic for me, as we're pursuing a solution that demonstrates the performance, high degree of connectivity and integration that's typically associated with TSVs, while maintaining cost and manufacturability that is more consistent with state of the art 3D packaging techniques. <br />
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In the "It's a small world" category, the story features commentary from <a href="http://www.3mts.com/3mtsAboutUs_Bill.html" title="3MTS: Bill Bottoms, Chairman and CEO" target="_blank">Dr. Bill Bottoms</a>, the presenter at the <a href="http://4dchips.blogspot.com/2010/03/ieee-cpmt-scv-meeting-report-3d-ic.html" title="" target="_blank">IEEE CPMT-SCV Meeting - 3D IC Integration: The Next Generation of Electronics</a> back in March of this year. <br />
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Of course, the article contains the oft-heard refrain about mobile being the driver for this technology (with which I heartily agree): <br />
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<blockquote>So why the drive to push past all these challenges? In short, the mobile market is extremely enticing. In the past, standard cell phone technology called for added functionality, decreased size, extended battery life, and lower cost. "Ultimately, the goal there was to get cell phones into as many people's hands as we possibly could in the industry," said Dave Stepniak, manager of wafer-level packaging at Texas Instruments (TI). "And the industry did a great job there; there's about 4.6 billion people today that use cell phones, and that's a good percentage of the world population." <br />
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But the market gets even more lucrative for chipmakers heading into the market for smart phones and other mobile devices with further increasing functionality. The silicon content in a smart phone could total more than $70, Stepniak said, compared with just a few dollars for a standard cell phone. "So it's a good market space for the semiconductor; it's very healthy for us, and it's a growing market," he said, adding that the smart phone market is expected to grow from approximately 250 million units to approximately 450 million units over the next couple years. <br />
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Besides increased memory capacity and bandwidth, the new consumer technologies require lower operating voltages to increase battery life, higher frequencies, and increased I/Os. In terms of die size, not only are x and y important, but also height. Devices are getting thinner and thinner, creating additional challenges with warpage on the package side. <br />
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"What we see as we move forward relative to the increasing frequencies is that the wire bond is running out of steam," Stepniak noted. "As you go above 1 GHz, you start to go to flip chip because of the parasitics that start to play within that package." Flip chip, however, is beginning to push the limits of I/O density, prompting designers to explore new packaging possibilities.</blockquote><br />
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The <a href="http://www.edn.com/article/510248-Wafer_level_packaging_pushes_past_new_mobile_demands.php" title="EDN: Wafer-level packaging pushes past new mobile demands" target="_blank">discussion</a> includes coverage of die embedding and fine pitch copper pillars (pitches to 50 µm are on their, courtesy of TI). It's well worth a read, and please keep watching us as we're hoping to be able to reveal more details regarding our work very soon.<br />
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Happy Stacking! <br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-59894886579402256612010-07-28T12:49:00.000-07:002010-07-28T12:49:10.445-07:00Farewell Tier Logic - We hardly knew youI'm quite disheartened by the report that <a href="http://4dchips.blogspot.com/2010/03/tier-logic-uncloaks-its-3d-fpga-company.html" title="Going Vertical: Tier Logic Uncloaks – It’s a 3D FPGA Company!" target="_blank">Tier Logic</a> has <a href="http://www.eetimes.com/electronics-news/4204843/FPGA-startup-Tier-Logic-folds" title="EETimes: FPGA startup Tier Logic folds" target="_blank">gone the way</a> of so many other promising FPGA startups.<a name='more'></a> <br />
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Just four months after emerging from stealth mode, <a href="http://4dchips.blogspot.com/2010/03/tier-logic-uncloaks-its-3d-fpga-company.html" title="Going Vertical: Tier Logic Uncloaks – It’s a 3D FPGA Company!" target="_blank">Tier Logic</a> has apparently joined the long list of promising FPGA ventures that couldn't make it work. For those who don't like to follow links, the gist of it is that Tier Logic was developing FPGAs with the programming circuitry stacked in a layer above the base arrays. This allowed for higher density, and (presumably) better performance. Unfortunately, according to the <a href="http://www.eetimes.com/electronics-news/4204843/FPGA-startup-Tier-Logic-folds" title="EETimes: FPGA startup Tier Logic folds" target="_blank">news in EETimes</a>: <br />
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<blockquote>"Despite the fact that we had only spent less than $20 million, we couldn’t get a lead investor to come in to a series B funding round," Hollingworth wrote in an email to <a href="http://www.eetimes.com/" title="EETimes site" target="_blank">EETimes</a>. <br />
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Hollingworth described the failure to secure funding as "an interesting comment on the market right now." While record revenues and profits are being reported by the likes of programmable logic suppliers Xilinx Inc. and Altera Corp., as well as other chip large companies like Intel Corp. and Texas Instruments Inc., venture capitalists have seen very few successful exits from chip companies over the past few years and are "therefore extremely reluctant to invest in startups, even ones that had made the progress we had," Hollingworth wrote. </blockquote><br />
While we are certainly taking a different approach to developing better FPGAs, it's still sad to see such a spectacular flame out. Especially since, such a short time ago, the company was full of confidence and optimism. This doesn't bode well for the rest of us that are out there hoping to, eventually, raise a few pennies to help our own ventures get going… <br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-48624373225946845022010-06-07T12:58:00.000-07:002010-06-07T13:09:47.263-07:00TSMC Vaporware: 3-D "Ecosystem"<a href="http://www.eetimes.com/" title="EETimes site" target="_blank">EETimes</a> reports that <a href="http://www.tsmc.com/" title="TSMC Home" target="_blank">TSMC</a> is:<br />
<blockquote>"… <a href="http://www.eetimes.com/225402091" title="EETimes: TSMC adds 3-D, ESL to platform efforts" target="_blank">putting the pieces in place to enable 3-D designs based on silicon interposers and through silicon vias (TSVs).</a>"</blockquote><a name='more'></a>This sounds very encouraging, until you get down into the <a href="http://www.eetimes.com/225402091" title="EETimes: TSMC adds 3-D, ESL to platform efforts" target="_blank">article</a> just a bit further...<br />
<blockquote>As part of the new efforts in its platform, TSMC is putting the pieces in place for a 3-D IC design methodology. First, TSMC is developing a design methodology for a silicon interposer technology. Then, it will have a TSV capability.<br />
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TSMC is not offering a silicon interposer or TSV manufacturing capability--yet. It is merely putting together the ecosystem and design tools, Quan said. ''We are putting the pieces in place,'' he said, but ''some of the pieces (for 3-D) are not there.''</blockquote>Ahh, now I understand. Someone in marketing at TSMC has noticed the recent excitement around 3-D, and they jumped on the bandwagon with this announcement. Perhaps their next press release will claim that they are preparing a "green 3-D politically correct ecosystem." That should cover all of the bases. TSMC certainly has the resources and stake in moving stacked die technology along faster. In that light, this announcement is pretty disappointing. Come on guys, step up. Some little birdies have been telling me that <a href="http://www.globalfoundries.com/" title="Global Foundries Home" target="_blank">Global Foundries</a> is already out ahead in bringing 3-D into mainstream production.<br />
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The TSMC <a href="http://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&language=E&newsid=4901" title="TSMC PR: TSMC Extends Open Innovation Platform" target="_blank">press release</a><br />
<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-34491315596197742082010-03-30T16:21:00.000-07:002010-03-30T16:25:54.737-07:00Elpida Prepping for 3-D Commercialization<a href="http://www.semiconductor.net/" title="Semiconductor International site" target="_blank">Semiconductor International</a> has a very informative <a href="http://www.semiconductor.net/article/454625-Elpida_Preparing_3_D_Commercialization.php" title="Semiconductor International: Elpida Preparing 3-D Commercialization" target="_blank">story</a> regarding 3-D directions at <a href="http://www.elpida.com/en/index.html" title="Elpida Memory, Inc. site" target="_blank">Elpida Memory, Inc.</a><a name='more'></a><br />
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<blockquote>"In a recent interview with Nikkei Microelectronics, Takao Adachi, the Elpida CTO in charge of new technology development, indicated that Elpida is looking to use its 3-D TSV technology to expand beyond its DRAM business and supply system solutions developed by stacking memory with RF, sensor or logic devices that would come from partner companies. Although the interview indicated that commercial 3-D devices would be shipped in 2010, very little detail was revealed about the 3-D IC process itself. "</blockquote><br />
<div style="text-align: center;"><a href="http://www.semiconductor.net/article/454625-Elpida_Preparing_3_D_Commercialization.php" target="_blank"><img src="http://www.semiconductor.net/photo/261/261106-Elpida_has_described_an_8_Gb_DRAM_product_with_eight_die_connected_by_TSVs_.jpg" alt="Elpida 8Gb DRAM - 8 die with TSVs" title="Elpida 8 Gb DRAM" border="0" style="vertical-align:center; margin: 1.0em" width="540" /></a><p><em>Elpida's 8 Gb DRAM product with eight die connected by TSVs.</em></p></div><br />
Read the rest of the interview <a href="http://www.semiconductor.net/article/454625-Elpida_Preparing_3_D_Commercialization.php" title="Semiconductor International: Elpida Preparing 3-D Commercialization" target="_blank">here…</a><br />
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As we've been predicting, 2010 seems to be shaping up as the year of broad commercialization for 3-D technology.<br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-54289513373298524892010-03-30T16:01:00.000-07:002010-03-30T16:05:25.367-07:00Applied Materials Announces New Equipment for 3-D<a href="http://www.appliedmaterials.com/" title="Applied Materials site" target="_blank">Applied Materials</a> recently put out a <a href="http://www.businesswire.com/news/appliedmaterials/20100329005479/en/Applied-Materials-Introduces-Critical-Liner-Technology-3D" title="Press Release: Applied Materials Introduces Critical Via Liner Technology for 3D Chip Packaging" target="_blank">press release</a> to announce some very interesting new equipment for 3-D fabrication. The <a href="http://www.appliedmaterials.com/products/producer_invia_4.html" title="Applied Producer InVia page" target="_blank">Applied Producer® InVia™</a> dielectric deposition system uses CVD to deposit the oxide liner for TSVs. The company claims that their new equipment:<a name='more'></a><br />
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<blockquote>"… has much higher throughput than batch furnaces, with the capability to process up to eight times more wafers per hour at less than half the cost, especially when depositing very thick liners for high performance applications. Competing PECVD systems are unable to deposit oxide films evenly in deep, narrow vias, making this approach unsuitable for HAR (High Aspect Ratio) applications."</blockquote><br />
<a href="http://www.eetimes.com/" title="EETimes site" target="_blank">EETimes</a> has a more comprehensive <a href="http://www.eetimes.com/224200614" title="EETimes: Applied rolls tool for 3-D chips" target="_blank">story</a> on the new gear.<br />
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This is one more bit of evidence that 3-D is moving out of the lab, and into the mainstream of commercial semiconductor products.<br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-86983479313521829032010-03-23T13:55:00.000-07:002010-03-23T15:14:10.322-07:00SanDisk 32GB microSDHC - Stack of 8 4GB dieMostly, I'm sharing this <a href="http://www.wired.com/gadgetlab/2010/03/32gb-microsd-card" title="Wired: You Could Easily Swallow This 32-GB MicroSD Card" target="_blank">story</a> because of the cool photo that <a href="http://www.wired.com/gadgetlab/" title="WIRED GADGET LAB" target="_blank">Wired's GadgetLab</a> included. The basic news is that <a href="http://www.sandisk.com/" title="SanDisk site" target="_blank">SanDisk</a> has <a href="http://investor.sandisk.com/phoenix.zhtml?c=86495&p=irol-newsArticle&ID=1404574&highlight=" title="Press Release: SanDisk First to Ship 32 Gigabyte microSDHC Card" target="_blank">announced</a> a 32 GByte microSDHC card. They used a 32 nm process <em>(cool symmetry — 32 billion bytes and 32 billionths of a meter)</em> and arranged the die in an 8 high stack of 4 GB die. Apparently the suggested retail price is around US$200.<a name='more'></a><br />
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Here's the photo that Wired included:<br />
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<div style="text-align: center;"><a href="http://www.wired.com/images_blogs/gadgetlab/2010/03/32nm_x3.jpg" target="_blank"><img src="http://www.4dchips.com/images/32nm_x3.png" alt="32-nm X3 chip under an electron microscope that shows eight-die stack. This is an actual photo of a 32nm X3 card that was torn apart to show the layers of memory chips inside. " title="Samsung 32GB microSDHC card, cut open, in cross section" border="0" style="vertical-align:center; margin: 1.0em" width="540" /></a></div><br />
<blockquote>32nm X3 chip under an electron microscope that shows eight-die stack. This is an actual photo of a 32nm X3 card that was torn apart to show the layers of memory chips inside.</blockquote><br />
Exciting stuff!<br />
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<em>Note: The <a href="http://www.wired.com/images_blogs/gadgetlab/2010/03/32nm_x3.jpg" title="32-nm X3 chip image on Wired's site - won't display in IE" target="_blank">original image</a> from Wired wouldn't display properly in IE, so I cached a version that IE could handle. The original is <a href="http://www.wired.com/images_blogs/gadgetlab/2010/03/32nm_x3.jpg" title="32-nm X3 chip image on Wired's site - won't display in IE" target="_blank">here</a>. The full size cached version is <a href="http://www.4dchips.com/images/32nm_x3.png" title="32-nm X3 chip image cached - should display fine in IE" target="_blank">here</a>.</em><br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-80905379171294823982010-03-22T17:39:00.000-07:002010-03-22T18:11:18.709-07:00IMAPS Conference - Great Stuff!The International Microelectronics and Packaging Society (<a href="http://www.imaps.org/" title="International Microelectronics and Packaging Society site" target="_blank">IMAPS</a>) recently wrapped up their <a href="http://www.imaps.org/devicepackaging/" title="IMAPS 6th Conference and Exhibition" target="_blank">6th International Conference and Exhibition on Device Packaging</a>. For those of us that couldn't swing a week in <a href="http://www.scottsdalecvb.com/" title="Scottsdale Visitors Bureau" target="_blank">Scottsdale</a>, we can thank <a href="http://4dchips.blogspot.com/2010/02/great-blog-perspectives-from-leading.html" title="Dr. Phil Garrou's Blog: Perspectives from the Leading Edge" target="_blank">Dr. Phil Garrou</a>, the event's General Chair, and well known 3D technology expert, for posting a great <a href="http://www.semiconductor.net/article/453765-IMAPS_Experts_Debate_3_D_Cost_Challenges-full.php" title="Semiconductor International: IMAPS Experts Debate 3-D Cost Challenges" target="_blank">synopsis</a>. Some of the key points include:<a name='more'></a><br />
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<blockquote>While several 3-D IC manufacturing programs are expected to ramp beginning in 2012, experts agree that challenges remain in materials selection, design, test and other critical areas.</blockquote><br />
That sounds good, but the slope of the adoption curve may be a bit more gentle than some of us hope…<br />
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<blockquote>… projection sees 3-D TSVs growing to 12% of the overall $59B IC package market by 2020.</blockquote><div style="text-align: center;"><a href="http://www.semiconductor.net/article/453765-IMAPS_Experts_Debate_3_D_Cost_Challenges-full.php" title="Semiconductor International: IMAPS Experts Debate 3-D Cost Challenges" target="_blank"><img alt="Chart of TSV Market Penetration" title="While TSV penetration will be relatively small in 2014, it will account for 12% of IC packaging by 2020" border="0" style="vertical-align:center; margin: 1.0em" src=" http://www.semiconductor.net/photo/259/259507-While_TSV_penetration_will_be_relatively_small_in_2014_it_will_account_for_12_of_IC_packaging_by_2020_Source_Prismark.jpg" width="540" /></a></div><br />
We've been having internal discussions regarding the availability of EDA tools that can effectively address vertical integration, so I was interested in the suggestion that:<br />
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<blockquote>Design is viewed as a 3-D infrastructure segment that is coming along, albeit slowly.</blockquote><br />
<a href="http://4dchips.blogspot.com/2010/03/ieee-cpmt-scv-meeting-report-3d-ic.html" title="Going Vertical: 3D IC Integration Meeting" target="_blank">Dr. Bottoms might disagree</a>, and based on what I've seen, I'm more aligned with Dr. Bottoms' position.<br />
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Dr. Garrou shares lots of other good stuff. It's well worth your time to take a look at his <a href="http://www.semiconductor.net/article/453765-IMAPS_Experts_Debate_3_D_Cost_Challenges-full.php" title="Semiconductor International: IMAPS Experts Debate 3-D Cost Challenges" target="_blank">report</a>.<br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-68000557739053247392010-03-22T17:15:00.000-07:002010-03-22T17:15:54.063-07:00Quantum Film - CMOS Image Sensor Killer?This is kind of off topic, but since image sensors are among the first commercial success stories for vertical integration, I thought that it was worth noting. <a href="http://www.invisageinc.com/Default.aspx" title="InVisage Technologies site" target="_blank">InVisage Technologies, Inc.</a> has announced the development of a "quantum film" that represents a dramatic improvement over current technologies. According to the <a href="http://www.eetimes.com/224000253" title="Quantum film threatens to replace CMOS image chips" target="_blank">story</a> in <a href="http://www.eetimes.com/" title="EETimes site" target="_blank">EETimes</a>, the InVisage process involves <a href="http://www.eetimes.com/190500733" title="EETimes: Nanocrystalline circuitry gets sprayed on " target="_blank">suspending lead-sulfide nanoparticles in a polymer matrix</a>. Here's the pertinent bit from the story:<a name='more'></a><br />
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<blockquote>The new semiconducting material was invented by Univeristy [<em>sic</em>] of Toronto professor Ted Sargent, who is now chief technology officer at InVisage. Sargent perfected a method of <a href="http://www.eetimes.com/190500733" title="EETimes: Nanocrystalline circuitry gets sprayed on " target="_blank">suspending lead-sulfide nanoparticles in a polymer matrix</a> to form a new class of semiconducting polymer that Invisage has spent the last three years integrating into a standard CMOS process. Now it can paint quantum film atop a low-cost wafer that has the electrode array for super-dense high-pixel-count images, but without any of the expensive CMOS photodetectors that make up the bulk of conventional digital camera sensors.</blockquote><br />
And, yes, I realize that titles of this post and the EETimes story are both hopelessly misleading, at least from a system perspective. InVisage's quantum film could replace the CMOS photon detectors. However, unless I'm really missing something in the story, it won't replace the rest of the circuitry required to collect, and process, the resulting electrons.<br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-51650140976759121622010-03-17T12:28:00.000-07:002010-03-17T12:28:05.115-07:00Novellus & IBM Form Cu TSV Joint Dev ProgramThis <a href="http://ir.novellus.com/releasedetail.cfm?ReleaseID=452400" title="Novellus Press Release: NOVELLUS SYSTEMS ANNOUNCES JOINT DEVELOPMENT PROGRAM ON COPPER THROUGH-SILICON-VIA (TSV) FOR 3-D SEMICONDUCTOR INTEGRATION" target="_blank">press release</a> from <a href="http://www.novellus.com/default.aspx" title="Novellus Systems Inc. site" target="_blank">Novellus</a> flashed across my screen today. Apparently they have set up a joint effort with IBM to commercialize a Cu TSV process using:<a name='more'></a><br />
<br />
<blockquote>… Novellus' SABRE copper electroplating and VECTOR plasma-enhanced chemical vapor deposition (PECVD) systems. The new process will enable the 3-D integration of multiple semiconductor chips in advanced product applications that require both small form factors and lower power consumption.</blockquote><br />
The release goes on to let us know that:<br />
<br />
<blockquote>Novellus has developed a unique, high performance SABRE Electrofill TSV process that uses patented hardware and chemistries to achieve void-free fill with minimal excess copper deposition. Copper overburden is reduced by 75 percent, allowing conventional chemical-mechanical polishing (CMP) to be used instead of custom polishing slurries. Additionally, SABRE's optimized TSV chemistries have faster plating times, resulting in higher throughputs. To address the requirement of lower temperature dielectrics, Novellus' VECTOR platform with its patented multi-station sequential deposition architecture (MSSD) enables the deposition of stable dielectric films at temperatures less than 200 degrees C with the breakdown voltage, leakage performance, and wafer-to-wafer repeatability required for reliable, high yielding TSVs.</blockquote><br />
I can't help but wondering whether these developments will be somewhat along the lines of what's going on over at <a href="http://www.tezzaron.com/" title="Tezzaron Semiconductor site" target="_blank">Tezzaron</a> with their "<a href="http://www.tezzaron.com/technology/FaStack.htm" title="Tezzaron FaStack Technology" target="_blank">Super Vias</a>" (there are some good papers describing Tezzaron's <a href="http://www.tezzaron.com/about/papers/ieee_vmic_2004_finalsecure.pdf" title="Tezzaron: Techniques for Producing 3D ICs with High-Density Interconnect (PDF, 4.0MB)" target="_blank">Cu Electrochemical Plating process</a> on their site). This is getting really interesting. As <a href="http://www.linkedin.com/pub/dick-wilson/2/9a3/186" title="Dick Wilson's Profile on LinkedIn" target="_blank">Dick Wilson</a> recently commented, this is going to be a patent war.<br />
<br />
Now that I'm paying attention, again thanks to Mr. Wilson, I'm seeing Big Blue's name all over the vertical integration space. Hmm…<br />
<br />
<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-11525660383708292752010-03-16T18:25:00.000-07:002010-03-16T18:29:13.558-07:00IBM Chilling Chip Stacks with Fluid in Microchannels<a href="http://www.eetimes.com/" title="EETimes site" target="_blank">EETimes</a> has a very interesting <a href="http://www.eetimes.com/223800313" title="EETimes: IBM and partners to cool 3-D IC stacks with microfluids" target="_blank">story</a> about work at IBM, along with École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH). They're using fluids (including, perhaps, water) passing through 50 µm diameter microchannels to cool stacked die.<a name='more'></a><br />
<br />
This sounds similar to the <a href="http://gtresearchnews.gatech.edu/newsrelease/cooling.htm" title="Georgia Tech: Beating the Heat: Liquid Cooling Technique Uses Microfluidic Channels Integrated onto the Backs of Chips" target="_blank">excellent work</a> that has been going on for several years at <a href="http://www.gatech.edu/" title="Georgia Institute of Technology site" target="_blank">Georgia Tech</a>. <a href="http://www.linkedin.com/in/deepaksekar" title="Deepak Sekar's profile on LinkedIn" target="_blank">Dr. Deepak Sekar</a> gave a presentation on the research at the recent <a href="http://4dchips.blogspot.com/2010/02/ieee-scv-eds-symposium-3d-interconnect.html" title="Going Vertical: IEEE SCV EDS 3D Interconnect Symposium" target="_blank">IEEE SCV EDS 3D Interconnect Symposium</a>. And Georgia Tech has a nice picture:<br />
<div style="text-align: center;"><a href="http://gtresearchnews.gatech.edu/images/cooling116.jpg" title="Georgia Tech: Microchannels on a Wafer" target="_blank"><img alt="Georgia Tech's Microchannels on a Wafer" title="Georgia Tech: Microchannels on a Wafer" border="0" style="vertical-align:center; margin: 1.0em" src=" http://gtresearchnews.gatech.edu/images/cooling116.jpg" width="540" /></a></div><br />
These developments are exciting because they represent an approach, albeit a fairly complicated one, to address the thermal management challenges presented by stacked die architectures. I'm not sure whether this methodology will ever turn out to be cost effective for mainstream systems, and it will most likely never be the answer for mobile devices. However, it's certainly viable for high end fixed location applications. For the others, we'll probably have to focus more on reducing power and leakage.<br />
<br />
I was also interested to note that the IBM work is targeting connection densities up to 10K connections per mm<sup>2</sup>.<br />
<br />
It's comforting to see that the big guns, like these organizations, are actively pursuing solutions to the real challenges of vertical integration.<br />
<br />
<br />
<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-40734154551157777312010-03-11T19:30:00.000-08:002010-03-11T19:30:06.702-08:00IMEC Using Synopsys TCAD Simulation ToolsAfter my <a href="http://4dchips.blogspot.com/2010/03/ieee-cpmt-scv-meeting-report-3d-ic.html" title="IEEE CPMT-SCV Meeting Report - 3D IC Integration: The Next Generation of Electronics" target="_blank">recent blurb</a> regarding the readiness of design tools to tackle 3D integration, I feel like I need to present at least some of the other side.<a name='more'></a><br />
<br />
<a href="http://www.edadesignline.com/" title="EDA DesignLine site" target="_blank">EDA DesignLine</a> is <a href="http://www.edadesignline.com/223300028" title="EDA DesignLine: IMEC, Synopsys to boost 3D stacked IC development" target="_blank">reporting</a> that <a href="http://www2.imec.be/be_en/home.html" title="IMEC home" target="_blank">IMEC</a> is using <a href="http://www.synopsys.com/Tools/TCAD/Pages/default.aspx" title="Synopsys: TCAD Process and Device Simulation Tools" target="_blank">Synopsys TCAD process and device simulation tools</a> to:<br />
<br />
<blockquote>… model the TSVs in the chip stacks to optimize 3D stacked IC performance and reliability.</blockquote><br />
The story suggests that:<br />
<br />
<blockquote>This collaboration, IMEC and Synopsys said, aims to accelerate the development of TSV technologies and to facilitate the adoption of 3D stacked ICs in the semiconductor industry.</blockquote><br />
This is all nice, and the TCAD tools clearly provide value for IMEC, but I stand by my previous assertion that the EDA vendors don't have anything approaching a complete flow that fully addresses the range design challenges in 3D.<br />
<br />
These IMEC guys are all over this technology, though. They even attended the <a href="http://4dchips.blogspot.com/2010/03/ieee-cpmt-scv-meeting-report-3d-ic.html" title="IEEE CPMT-SCV Meeting Report - 3D IC Integration: The Next Generation of Electronics" target="_blank">IEEE CPMT-SCV: 3D IC Integration meeting</a> last night and announced that they are hiring for positions in Leuven, Belgium. They sold it hard, going so far as to point out that Leuven is the home of <a href="http://www.stellaartois.com/en-be/home.html" title="Stella Artois site" target="_blank">Stella Artois</a>.<br />
<br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-44572032283075051972010-03-11T17:20:00.000-08:002010-07-28T11:57:06.744-07:00Tier Logic Uncloaks – It’s a 3D FPGA Company!Just as I was getting ready to head over to the <a href="http://4dchips.blogspot.com/2010/03/ieee-cpmt-scv-meeting-report-3d-ic.html" title="Going Vertical: Meeting Report - 3D IC Integration" target="_blank">IEEE CPMT-SCV 3D IC Integration meeting</a> last night, this fascinating story popped up. <a href="http://www.tierlogic.com/" title="Tier Logic site" target="_blank">Tier Logic</a>, a Santa Clara 3D FPGA venture has finally dropped their <a href="http://en.wikipedia.org/wiki/Cloak_of_invisibility" title="Wikipedia: Cloak of Invisibility" target="_blank">cloak of invisibility</a> to reveal another 3D FPGA company.<a name='more'></a><br />
<br />
Because I'm more than a little lazy (and I don't get paid to blog), permit me to quote from <a href="http://www.edn.com/blogger/2391.html" title="EDN: About Ron Wilson" target="_blank">Ron Wilson</a>'s excellent <a href="http://www.edn.com/blog/Practical_Chip_Design/37833-TierLogic_lifts_the_veil_another_take_on_the_3D_FPGA.php" title="TierLogic lifts the veil: another take on the 3D FPGA" target="_blank">post</a> over on <a href="http://www.edn.com/" title="EDN site" target="_blank">EDN</a>:<br />
<br />
<blockquote>TierLogic's big idea is elegant and audacious: increase the density of FPGAs by moving all the configuration memory—not the data memory or the look-up-table (LUT) memory, but the RAM cells that control the interconnect muxes—out of the silicon. Removing these memory bits by itself can cut die area—at least the die area occupied by logic fabric—more than in half, according to the company's vice president of sales and marketing, Paul Hollingworth. TierLogic employs this advantage to use a mature 90nm process node and still deliver a smaller die area than a conventional SRAM FPGA would require, making it possible to offer the FPGAs at about half the cost of equivalent conventional parts.<br />
<br />
But those SRAM cells have to go somewhere. That's where TierLogic's foundry partner Toshiba comes into the picture. Toshiba has developed a unique back-end-of-line process that puts a layer of amorphous-silicon thin-film transistors (TFTs) on top of the interconnect stack. The proprietary process uses virtually none of the wafer's thermal budget, so it's compatible with advanced CMOS. Yet at 180nm dimensions Toshiba can produce sufficiently fast and dense TFT SRAM cells to accommodate all the configuration memory required for the FPGA below. And since the configuration SRAM just sits there providing steering bits to the muxes—no user delay paths pass through the configuration memory—the slower, more stable TFT SRAM has no impact on user timing, except for the significant benefit of allowing the active die area be much smaller.</blockquote><br />
<div style="text-align: center;"><a href="http://www.tierlogic.com/uploads/press-room-files/Tier-Logic-3D-TierFPGA-and-TierASIC-Technology-Brief.pdf" imageanchor="1" title="Tier Logic Technology Illustration (PDF)"><img alt="Illustration of Tier Logic Technology" title="Tier Logic Technology Illustration" border="0" style="vertical-align:center; margin: 1.0em" src=" https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEggVtXYOTIjohuAl7hQ6AY5Q9BNM49ja7m8tznjyyhy5EmqDj-A1kTHQmL_YI3qsusTkdz4TDxuF8FpO2IUC92e0OrgTJma5_4s3Hhj6Fkyk7o_mhQpMeIqeTamDf4ItRaOLpdRBT08QiI/s320/TierLogic.png" width="410" /></a></div><br />
Mr. Wilson goes on to observe that this approach not only provides much better density (as much as 3x standard FPGAs), but that it provides a very quick, and accurate, path to creating mask-programmed devices. If you're interested in the subject, you should check out the <a href="http://www.edn.com/blog/1690000169/post/1870053187.html" title="TierLogic lifts the veil: another take on the 3D FPGA" target="_blank">original post</a>. There's also a <a href="http://www.eetimes.com/223400002" title="EETimes: FPGA startup: Process tech eases ASIC migration" target="_blank">story in EETimes</a>.<br />
<br />
Using TFT's for the configuration memory is a fascinating approach. <a href="http://www.4dchips.com/" title="4D Chips site" target="_blank">4D Chips</a> has looked at similar architectures, where the configuration memory was actually in a second die (conceptually, we're thinking more along the lines of the work going on over at <a href="http://4dchips.blogspot.com/2010/02/nupga-leverages-3d-stacks-to.html" title="Going Vertical: NuPGA Leverages 3D Stacks to Revolutionize Programmable Logic" target="_blank">NuPGA</a>), but the Tier Logic architecture is certainly intriguing.<br />
<br />
By the way, as Mr. Wilson ably points out, Both NuPGA and Tier Logic are developing FPGAs that leverage vertical integration. The third dimension in the recent <a href="http://www.tabula.com/news/news_03-01-2010.php" title="Tabula PR: Tabula Introduces Breakthrough Spacetime Programmable Logic Architecture" target="_blank">announcement</a> from <a href="http://www.tabula.com/" title="Tabula site" target="_blank">Tabula</a> is <strong><em>time</em></strong>, not stacked die. I was going to do a post about Tabula, but it doesn't ever seem to bubble up on the priority list. Just in case it never does, <a href="http://www.eetimes.com/" title="EETimes site" target="_blank">EETimes</a> has an <a href="http://www.eetimes.com/223100910" title="EETimes: 3-D architecture promises new type of PLD" target="_blank">excellent article</a> describing the company and the technology.<br />
<br />
This is certainly an exciting time for 3D.<br />
<br />
<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-10971139617279561172010-03-11T13:55:00.000-08:002010-03-15T17:00:07.715-07:00IEEE CPMT-SCV Meeting Report - 3D IC Integration: The Next Generation of Electronics (Updated)The <a href="http://www.cpmt.org/scv/" title="IEEE CPMT-SCV site" target="_blank">IEEE Components, Packaging and Manufacturing Technology Society, Santa Clara Valley Chapter</a> put together a great program last night: "<a href="http://www.cpmt.org/scv/meetings/cpmt1003.html" title="CPMT-SCV: 3D IC Integration meeting page" target="_blank">3D IC Integration: The Next Generation of Electronics</a>." The speaker, <a href="http://www.3mts.com/3mtsAboutUs_Bill.html" title="3MTS: Bill Bottoms, Chairman and CEO" target="_blank">Dr. W. R. Bottoms</a>, did a wonderful job of illuminating the current state of the industry. He clearly shares the excitement that we've been blogging about. I even managed to pick up some interesting tidbits by paying attention to the conversations at the meeting.<a name='more'></a><br />
<br />
<a href="http://www.3mts.com/3mtsAboutUs_Bill.html" title="3MTS: Bill Bottoms, Chairman and CEO" target="_blank">Dr. W. R. Bottoms</a>, Chairman, <a href="http://www.3mts.com/" title="Third Millennium Test Solutions site" target="_blank">Third Millennium Test Solutions</a>, gave a great presentation at the event. Some of the highlights, for me, included:<br />
<ul><li>For some products, packaging and test make up more than 2/3 of the final cost. The actual die in the package might account for less than 30% of the final cost.<br />
</li>
<li>Consumer electronics is driving the semiconductor market, and consumers are demanding devices that do a better job of interacting with people.<br />
</li>
<li>The near term driving forces for Vertical Integration include:<br />
<ul><li>Miniaturization — (reduced volume and weight)</li>
<li>Increased performance</li>
<li>Reduced power consumption</li>
<li>Mixed functional integration</li>
</ul></ul><ul><li>Longer term, reduced cost will also be an important driving force.</li>
<li>Everything (Architectures, Materials, Processes, …) is changing.</li>
<li>Dr. Bottoms asserts that the semiconductor industry's future growth depends on vertical integration.</li>
<li>The concept of "Known Good Die" will be replaced by "<strong><em>Probably</em></strong> Good Die."</li>
<li>Transistors are fast enough, and efficient enough. Interconnect dominates speed & power constraints. Vertical integration is the most straightforward way to minimize interconnect. For "n" stacked layers, interconnect decreases by the square root on "n" (sorry, I couldn't figure out how to represent the symbol in blogger).</li>
<li><a href="http://www.elpida.com/en/index.html" title="Elpida Memory, Inc. site" target="_blank">Elpida</a> has a 3-D DDR3 memory module, based on TSV, with 9 layers (8 memory die and 1 memory controller). The current generation product has an 8Gbit capacity, with a 16Gbit product coming in April (Unfortunately, I couldn’t find the part on their <a href=" http://www.elpida.com/en/products/ddr3module.html " title="Elpida DDR3 Modules page" target="_blank">products page</a>). <a href="http://www.samsung.com/global/business/semiconductor/productList.do?fmly_id=691&xFmly_id=690" title="Samsung DDR3 DRAM page" target="_blank">Samsung</a> is also coming along with a similar product.</li>
<li>We have found, or soon will find, solutions to address each of the <a href="http://4dchips.blogspot.com/2010/02/ieee-scv-eds-symposium-3d-interconnect.html" title="Going Vertical: 3D Interconnect - Shaping Future Technology" target="_blank">Four Horsemen</a></li>
<li><strong>We will see high volume commercial shipments of 3-D products in 2010</strong></li>
</ul><p>Some other interesting bits that I picked up include: <a href="http://www.micron.com/" title="Micron site" target="_blank">Micron</a> is developing 3-D fab technology for in-house use, and they are hiring for the effort in Boise. <a href="http://www2.imec.be/be_en/home.html" title="IMEC home" target="_blank">IMEC</a> is also hiring, if Belgium is your glass of <a href="http://www.stellaartois.com/en-be/home.html" title="Stella Artois site" target="_blank">Stella Artois</a>.</p><p>In response to a question from the audience, Dr. Bottoms acknowledged that current design tools are not up to the challenge of 3-D. They solve some parts of the problem, but none of the vendors have yet fielded a complete solution (although, all of the design tool vendors that I've talked with claim that their current suites fully address 3-D design). There is a real opportunity out there for my friends at <a href="http://www.cadence.com/us/pages/default.aspx" title="Cadence Design Systems site" target="_blank">Cadence</a>, <a href="http://www.mentor.com/" title="Mentor Graphics site" target="_blank">Mentor</a> and <a href="http://www.synopsys.com/home.aspx" title="" target="_blank">Synopsys</a>.</p><p>Pretty much everything that we heard at the meeting is in line with what we're seeing as we move forward with <a href="http://www.4dchips.com/" title="4D Chips site" target="_blank">4D Chips</a>, so I really appreciated the discussion. The <a href="http://ewh.ieee.org/soc/cpmt/presentations/cpmt1003a.pdf" title="3D IC Integration: The Next Generation of Electronics (PDF 1.6 MB)" target="_blank">slides from the event</a> (PDF 1.6 MB) are posted up on the <a href="http://www.cpmt.org/scv/" title="IEEE CPMT-SCV site" target="_blank">IEEE CPMT-SCV site</a>. They're definitely worth a look.</p><hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-68703535920385626832010-03-05T20:53:00.000-08:002010-03-22T17:20:29.055-07:00Dr. Garrou on SEMI's Industry Strategy Symposium 2010One of the benefits of following sources like <a href="http://www.semiconductor.net/blog/Perspectives_From_the_Leading_Edge/" title="Perspectives From the Leading Edge blog" target="_blank">Perspectives From the Leading Edge</a> is that I get a peek into events that wouldn't allow a simple engineer like me through the venue doors.<a name='more'></a><br />
<br />
<a href="http://www.linkedin.com/pub/philip-garrou/16/7aa/831" title="Dr. Philip Garrou's Profile on LinkedIn" target="_blank">Philip Garrou</a> just <a href="http://www.semiconductor.net/blog/Perspectives_From_the_Leading_Edge/31299-IC_Consolidation_Node_Scaling_and_3D_IC.php?rssid=20238" title="Perspectives from the Leading Edge: IC Consolidation, Node Scaling and 3D IC" target="_blank">posted</a> about <a href="http://www.semi.org/en/index.htm" title="SEMI - Home page" target="_blank">SEMI</a>'s recent <a href="http://www.semi.org/en/EventsTradeshows/ExecutiveConferences/ctr_032223" title="ISS 2010 Event page" target="_blank">Industry Strategy Symposium</a> (ISS 2010).<br />
<br />
You really should just go read Dr. Garrou's <a href="http://www.semiconductor.net/blog/Perspectives_From_the_Leading_Edge/31299-IC_Consolidation_Node_Scaling_and_3D_IC.php?rssid=20238" title="Perspectives from the Leading Edge: IC Consolidation, Node Scaling and 3D IC" target="_blank">post</a>, but there were a couple of bits that particularly stood out for me.<br />
<br />
First, <a href="http://www.ibs-inc.net/" title="International Business Strategies, Dr. Jones' firm" target="_blank">Dr. Handel H. Jones</a>, who once was kind enough to do some consulting for one of my ventures when we were way too poor to pay him, and thus to whom I am forever in debt, suggested that:<br />
<blockquote>"…the cost per gate actually goes up at 22 nm"</blockquote><div style="text-align: center;"><a href="http://www.semiconductor.net/blog/Perspectives_From_the_Leading_Edge/31299-IC_Consolidation_Node_Scaling_and_3D_IC.php?rssid=20238" imageanchor="1" title="Dr. Handel Jones, IBS: Cost per Gate Increases at 22nm"><img border="0" style="vertical-align:center; margin: 1.0em" src="http://www.semiconductor.net/photo/256/256598-121_4.jpg" width="500" /></a></div><br />
That's right, it goes <strong><em>up</em></strong>. This puts even more wood behind the arrow of achieving higher functionality through vertical integration, rather than 2-D device scaling, as does the following.<br />
<br />
Dr. Garrou cites work from both NC State and Toshiba to reach the following conclusion:<br />
<blockquote>"… it is clear from all published results so far that 3D allows you to achieve improved performance at a higher node which translates into lower cost if and when 3D reaches the necessary cost points."</blockquote><br />
Seeing is believing so:<br />
<div style="text-align: center;"><a href="http://www.semiconductor.net/blog/Perspectives_From_the_Leading_Edge/31299-IC_Consolidation_Node_Scaling_and_3D_IC.php?rssid=20238" imageanchor="1" title="Prof. Paul Franzon, NC State: 3D IC Is Worth Two Generations of Scaling"><img border="0" style="vertical-align:center; margin: 1.0em" src="http://www.semiconductor.net/photo/256/256601-121_6.jpg" width="400" /></a><br />
<br />
<a href="http://www.semiconductor.net/blog/Perspectives_From_the_Leading_Edge/31299-IC_Consolidation_Node_Scaling_and_3D_IC.php?rssid=20238" imageanchor="1" title="Toshiba 16 Core Processor Shows Better Perf 1 Node Higher"><img border="0" style="vertical-align:center; margin: 1.0em" src="http://www.semiconductor.net/photo/256/256602-121_7.jpg" width="480" /></a></div><br />
Shifting away from ISS 2010…, <a href="http://www.4dchips.com/" title="4D Chips site" target="_blank">4D Chips</a> has been involved in a series of discussions recently that strongly suggest that 2010 will be the year when a whole raft of commercial products leveraging 3-D chips will hit the market. Unfortunately, I'm under NDA regarding the specifics, but I'm more convinced than ever that this is the year of vertical integration.<br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-26787393088763069072010-03-01T12:08:00.000-08:002010-03-01T15:05:32.395-08:00ALLVIA Integrates Embedded Capacitors into Silicon InterposersThe smart folks over at <a href="http://www.allvia.com/" title="ALLVIA site" target="_blank">ALLVIA</a> have integrated passive components directly into the silicon interposer that resides between the die and the substrate.<a name='more'></a><br />
<br />
According to their <a href="http://www.allvia.com/news/1002_integration_breakthrough.html" title=" ALLVIA Integrates Embedded Capacitors for Silicon Interposers and 3D Stacked Semiconductors" target="_blank">announcement</a>:<br />
<br />
<blockquote>"… TSV interposers with embedded capacitors provide the shortest electrical path between devices and power supply decoupling capacitors. TSVs with their very low inductance interconnects thus will enable very high electrical performance when integrated with embedded thin film capacitors.<br />
<br />
ALLVIA's silicon TSV interposers enable interconnect pitch matching between a high-density IC chip and an organic or a ceramic substrate. Further, they provide a very low stress interconnect to Si ICs that use low-k dielectrics. These benefits make ALLVIA's interposers an attractive solution for advanced packaging of next generation logic devices."</blockquote><br />
<a href="http://www.eetimes.com/" title="EETimes site" target="_blank">EETimes</a> covered the story <a href="http://www.eetimes.com/223100479" title="EETimes: TSV foundry embeds capacitors in interposers" target="_blank">here</a>.<br />
<br />
One more innovation that moves vertical integration nearer to the main stream…<br />
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<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-76559866862941899202010-02-26T22:10:00.000-08:002010-03-22T17:21:17.038-07:00Great Blog: Perspectives From the Leading EdgeI recently came across another great blog, "<a href="http://www.semiconductor.net/blog/Perspectives_From_the_Leading_Edge/" title="Perspectives From the Leading Edge blog" target="_blank">Perspectives From the Leading Edge</a>," that focuses on vertical integration technology.<a name='more'></a><br />
<br />
<a href="http://www.linkedin.com/pub/philip-garrou/16/7aa/831" title="Dr. Philip Garrou's Profile on LinkedIn" target="_blank">Philip Garrou</a>, Ph.D. (…and <a href="http://www.semiconductor.net/blog/profile/12939-Phil_Garrou.php" title="Dr. Philip Garrou's Profile on Semiconductor International" target="_blank">here</a>, if you don't like LinkedIn) writes a wonderfully insightful blog that covers the research and technology development in the space. I'm now a subscriber and dedicated reader. I've learned a lot from Dr. Garrou's previous posts.<br />
<br />
The blurb on the blog explains it better than I could:<br />
<blockquote>"Dr. Phil Garrou gives his perspective and insight into developments in 3-D integration and advanced packaging, reporting the latest technical goings on from conferences, conversations, and more."</blockquote><br />
Since most of us don't have the bandwidth do cover all of the developments and conferences, I encourage everyone out there to check out <a href="http://www.semiconductor.net/blog/Perspectives_From_the_Leading_Edge/" title="Perspectives From the Leading Edge blog" target="_blank">Dr. Garrou's blog</a>.<br />
<br />
<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-9835624561705233222010-02-19T21:08:00.000-08:002010-03-01T15:06:41.767-08:00Progress on Driving Down the Cost of TSVsThe cover story in <a href="http://www.semiconductor.net/" target="_blank" title="Semiconductor International site">Semiconductor International</a>'s <a href="http://www.semiconductor.net/archive/2010/20100201.php" target="_blank" title="Semiconductor International February 2010 Issue">February 2010</a> issue is <a href="http://www.semiconductor.net/article/449266-Driving_Down_the_Cost_of_TSVs.php" target="_blank" title="Semiconductor International: Driving Down the Cost of TSVs">Driving Down the Cost of TSVs</a>. The story provides good insight into the progress towards reducing the cost of the entire TSV process flow.<a name='more'></a><br />
<br />
If we remember that manufacturing cost is the first of the "<a href="http://4dchips.blogspot.com/2010/02/ieee-scv-eds-symposium-3d-interconnect.html" target="_blank" title="Going Vertical: IEEE SCV EDS Symposium: 3D Interconnect - Shaping Future Technology">Four Horsemen</a>" of vertical integration, this <a href="http://www.semiconductor.net/article/449266-Driving_Down_the_Cost_of_TSVs.php" target="_blank" title="Semiconductor International: Driving Down the Cost of TSVs">story</a> is especially compelling. The high cost of TSVs has been a barrier to adoption, but we're making significant progress. Three years ago, the calculated total cost of ownership for a 10K wafer start fab was running $320/wafer. The 2010/2011 target for the international Semiconductor 3-D Equipment and Materials Consortium (<a href="http://www.emc3d.org/" title="3-D Equipment and Materials Consortium site" target="_blank">EMC-3D</a>) is $120/wafer.<br />
<br />
Because I can't post without a couple of cool quotes, I wanted to highlight that:<br />
<blockquote>"Mass production of 3-D TSVs has already started in MEMS and CMOS image sensors, power applications are just beginning, and stacked DRAM modules are on track for 2010–2011."</blockquote>and, most importantly:<br />
<blockquote>"The level of activity in TSV suggests the performance improvements and cost reductions have combined to enable financial justification by many companies to begin aggressive development. Continued reduction of cost will increase the speed of adoption. Currently, the consortium sees at least 15 companies with TSV research or pilot production, and we expect many more to be added in 2010."<br />
</blockquote>Clearly, 2010 is the year of commercial exploitation of TSVs for vertical integration.<br />
<br />
Because I love illustrations, I wanted to close with this nice picture from the story. It shows a 3-D stack that [they suggest] closely resembles commercial chips of the future. It consists of a 25 µm thick logic die, with a commercial DRAM stacked on top, using TSVs and microbumps. (Source: IMEC)<br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="http://www.semiconductor.net/article/449266-Driving_Down_the_Cost_of_TSVs.php" title="Semiconductor International: Driving Down the Cost of TSVs" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEghViFaKU56WloTELl7Q59Ya3qiisLIi4C9pFNUqea0TugWB45Xzqz6d6_kmCv_3zrvOussnQPJz8nRSLe_Vx_k2npyaok78Pcr1jcO1vSrd_DMvCNlL0OOk2jNMoJVdSmpz-rYX6K9460/s640/3DStack.jpg" width="480" /></a></div><br />
<hr ...="" />Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-52395881553628277452010-02-17T19:27:00.000-08:002010-02-17T19:32:02.856-08:00IEEE: Design Challenges Loom for 3-D ChipsA very good <a href="http://spectrum.ieee.org/semiconductors/design/design-challenges-loom-for-3d-chips" title="IEEE Spectrum: Design Challenges Loom for 3-D Chips" target="_blank">overview</a> of the current state of TSV technology came out today on the <a href="http://spectrum.ieee.org/" title="IEEE Spectrum Site" target="_blank">IEEE Spectrum site</a>. The whole piece is well worth a read, and I strongly encourage everyone with an interest in the subject to check it out. The first illustration is priceless<a name='more'></a><br />
<br />
Although much of the article rehashes the "<a href="http://4dchips.blogspot.com/2010/02/ieee-scv-eds-symposium-3d-interconnect.html" title="Going Vertical: IEEE SCV EDS Symposium: 3D Interconnect - Shaping Future Technology" target="_blank">Four Horsemen</a>" of vertical integration: Manufacturing Cost, Test, Thermal Management and Design — it's still a valuable snapshot of developments in the technology. I especially appreciated the discussion of whether 3D assembly belongs with the foundry, the packaging house, or some (as yet) unnamed third participant.<br />
<br />
For me, the money quote is from <a href="http://si.epfl.ch/page30509.html" title="Dr. Marchal's Bio? They spelled the given name wrong." target="_blank">Pol Marchal</a>, a principal scientist of 3-D integration at <a href="http://www2.imec.be/be_en/home.html" title="IMEC English language site" target="_blank">IMEC</a> (Interuniversity Microelectronics Centre):<br />
<blockquote>"the industry pull for this technology is big. TSVs are expected to widely populate chips by 2012 or 2013"</blockquote><br />
Clearly, now is the time to start exploring this technology and working with organizations like <a href="http://www.4dchips.com/" title="4D Chips Site" target="_blank">4D Chips</a> to start preparing for the coming tidal wave of demand.<br />
<br />
In the meantime, here's a very cool picture of TSV's from IMEC:<br />
<br />
<a href="http://spectrum.ieee.org/semiconductors/design/design-challenges-loom-for-3d-chips" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="399" src="http://spectrum.ieee.org/image/1520103" width="464" /></a><br />
<br />
I just noticed that this <a href="http://spectrum.ieee.org/semiconductors/design/design-challenges-loom-for-3d-chips" title="IEEE Spectrum: Design Challenges Loom for 3-D Chips" target="_blank">story</a> was the top piece on the <a href="http://spectrum.ieee.org/" title="IEEE Spectrum Site" target="_blank">IEEE Spectrum site</a> today. I hope that there is some sort of statement about the importance of vertical integration in that honored placement.<br />
<br />
For those that were wondering, I have no idea why the reporter insists on writing "IMEC" as "Imec."<br />
<br />
<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-26911383674925574342010-02-12T15:56:00.000-08:002010-02-17T19:40:08.643-08:00ALLVIA Presentation: Through Silicon Vias - Design & ReliabilityI came across this excellent slide deck titled <strong><a href="http://ewh.ieee.org/soc/cpmt/presentations/cpmt0905a.pdf" title="Through Silicon Vias: Design and Reliability" target="_blank">Through Silicon Vias (TSV): <em>Design and Reliability</em></a></strong> (PDF) from our friends at <a href="http://www.allvia.com/" title="ALLVIA site" target="_blank">ALLVIA</a>, the TSV foundry specialists.<a name='more'></a><br />
<br />
It appears that the material was presented at an <a href="http://www.cpmt.org/scv/" title="IEEE CPMT-SCV site" target="_blank">IEEE Components, Packaging and Manufacturing Technology Society, Santa Clara Valley Chapter</a> event in May of 2009, so it may not reflect their current bleeding edge. However, I think that the material gives an excellent overview of TSV technology as well as a good introduction to the company. You should check this <a href="http://ewh.ieee.org/soc/cpmt/presentations/cpmt0905a.pdf" title="Through Silicon Vias: Design and Reliability" target="_blank">slide deck</a> out. The pictures alone more than justify a look!<br />
<br />
<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-84086861238129812662010-02-12T15:04:00.000-08:002010-02-17T19:39:43.412-08:00Exciting 3D IC Integration Event Coming Up!The <a href="http://www.cpmt.org/scv/" title="IEEE CPMT-SCV site" target="_blank">IEEE Components, Packaging and Manufacturing Technology Society, Santa Clara Valley Chapter</a> is putting together what promises to be an extremely interesting program titled, "<a href="http://www.cpmt.org/scv/meetings/cpmt1003.html" title="CPMT-SCV: 3D IC Integration meeting page" target="_blank">3D IC Integration: The Next Generation of Electronics</a>." The fun will commence at 6:00 PM on Wednesday, March 10, 2010, in Santa Clara.<a name='more'></a><br />
<br />
<a href="http://www.3mts.com/3mtsAboutUs_Bill.html" title="3MTS: Bill Bottoms, Chairman and CEO" target="_blank">Dr. W. R. Bottoms</a>, Chairman, <a href="http://www.3mts.com/" title="Third Millennium Test Solutions site" target="_blank">Third Millennium Test Solutions</a>, is the presenter. The overview for the talk is very much in line with the issues that we're addressing at <a href="http://www.4dchips.com/" title="4D Chips site" target="_blank">4D Chips</a>, so I'm really looking forward to it:<br />
<br />
<blockquote>The semiconductor industry has followed a path defined by Moore's Law for 40 years. This has resulted in unprecedented progress but we are clearly nearing the end of Moore's Law scaling. The concept of equivalent scaling and other changes to maintain that rate of progress have been defined as "More than Moore". The most important of these is 3D integration. Although there has been significant progress in development of 3D technologies it has not yet reached the high volume production mainstream. Recent progress such as the advent of 3D standards will result in the emergence of high volume 3D IC production in 2010. The major driving issues and challenges associated with 3D IC production and the outlook for future 3D integration will be discussed.</blockquote><br />
I'll be at both the dinner and the presentation. I'm looking forward meeting up with anyone else who plans to attend. Please come over to say, "Hi," and let me know what you think of this blog. I'll see you on the 10th!<br />
<br />
<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-20801002679820247422010-02-11T12:56:00.000-08:002010-02-17T19:39:14.532-08:00Semi-Therm Course: Cooling Challenges in 3D PackagingFor those, like me, that don't cast our info nets nearly wide enough, this event might have escaped our attention. That is unfortunate. The <a href="http://www.semi-therm.org/" title="Semi-Therm Site" target="_blank">26th Annual Thermal Measurement, Modeling and Management Symposium</a> is being held next week in Santa Clara. One course, "<strong><u>Cooling Challenges in 3D Packaging</u></strong>" is of particular interest to those who follow this humble blog. The short course will be presented by <a href="http://www-mae.uta.edu/faculty/agonafer.html" title="Dr. Agonafer page" target="_blank">Dereje Agonafer, Ph.D.</a> Dr. Agonafer is a Professor and Director, Elec, MEMS & Nanoelectronics Systems Packaging Center at the <a href="http://www.uta.edu/" title="University of Texas at Arlington site" target="_blank">University of Texas at Arlington</a> (<a href="http://www.uta.edu/ra/real/editprofile.php?pid=4" title="Agonafer's Faculty profile" target="_blank">Faculty profile</a>).<a name='more'></a><br />
<br />
I extracted the course abstract from the event's <a href="http://www.semi-therm.org/pdflib/st26ap.pdf">Advance Program</a>:<br />
<br />
<blockquote>The convergence of computing and communications dictates building up rather than out. As consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing, and integrating various functions into the same package is becoming more crucial. Over the past few years, die stacking has emerged as a powerful tool for satisfying these challenging Integrated Circuit packaging requirements. The first part of the course will be a review of electronic packaging based on the instructor's over 10 years of experience teaching a packaging course. This will be followed by an overview of 3D packaging and an in depth discussion of the thermo/mechanical challenges in stacked packaging based on the author's recently published papers. Package architectures evaluated in this presentation are rotated stack, staggered stack, stacking with spacers, stacks with thermal vias and package on package. Moving forward in more complex combinations such as stacking logic and memory, there is a desire to include thermal design in the upstream phase concurrently with the architecture design. In order to develop design guidelines for microprocessors based on both thermal and device clock performance, it is necessary to know the characteristics of each functional block on the die, guidelines of which are provided by the architectural team. For better thermal performance, the functional blocks are then repositioned and the resulting maximum temperatures are noted for all the cases. Recent studies at an attempt to a co-architectural design where design optimization is based on both thermal and architectural objectives will also be addressed.</blockquote><br />
The course looks like it will be <strong>extremely</strong> interesting. If anyone does have the opportunity to attend, I'd sincerely love to hear more about the information presented.<br />
<br />
<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0tag:blogger.com,1999:blog-2324819689028320996.post-85675454891003150622010-02-11T11:43:00.000-08:002010-02-17T19:38:51.823-08:00ISSCC Forum: Silicon 3D-Integration Technology and Systems<div style="text-align: left;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">I'm really mad at myself for not heading up to the <a href="http://www.isscc.org/" target="_blank" title="International Solid-State Circuits Conference site">ISSCC</a> this year. The conference featured a </span><b><i><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">full day</span></i></b><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> forum on 3D Integration. Although I'm sorry that I missed it, I'm thrilled by the attention, as it clearly demonstrates just how important this technology is becoming. I was particularly gratified to see a good mix of industry and academic interests involved in the 3D forum.</span><br />
<a name='more'></a><br />
<span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">There is one presentation that I'm especially disappointed about missing, "<b>3D TSVs - Ready for Design!</b>" from IMEC, appears to reinforce my assertion that 3D is real world technology that is well beyond the "science experiment" stage. We can design these systems, and we can build them!</span><br />
<span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"><br />
</span><br />
<span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">I excerpted the agenda from the <a href="http://www.isscc.org/isscc/2010/ap/" target="_blank" title="ISSCC 2010: Sensing the Future">program</a> and shared the result below. I also borrowed a <a href="http://www.4dchips.com/misc/ISSCC2010_3DIntegrationSession.pdf" target="_blank" title="ISSCC Forum Agenda: Silicon 3D-Integration Technology and Systems">page</a> <i>(PDF)</i> from the <a href="http://www.isscc.org/isscc/2010/ISSCC2010_AdvanceProgram.pdf" target="_blank" title="Advance Program: 2010 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - SENSING THE FUTURE">full advance program</a> <i>(PDF)</i> - the nicer formatting is a tad easier to read, if you don't mind the pdf.</span></div><div style="text-align: left;"><b><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"><br />
</span> </b></div><div style="text-align: left;"><div style="text-align: center;"><b><span style="font-size: large;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">F1: Silicon 3D-Integration Technology and System</span></span></b><span style="font-size: large;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">s</span></span></div></div><div style="text-align: left;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"><br />
</span></div><div><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Organizer:</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Pascal Urard</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">, </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">STMicroelectronics, Crolles, France</span></span></i></div><div><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"><br />
</span> </span></i></div><div><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Co-organizer:</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Ken Takeuchi</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">, </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">University of Tokyo, Tokyo, Japan</span></span></i></div><div><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"><br />
</span> </span></i></div><div><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Chair:</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Kerry Bernstein</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">, </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Applied Research Associates, South Royalton, VT</span></span></i></div><div><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"><br />
</span> </span></i></div><div><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Committee:</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Hideto Hidaka</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">, </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Renesas Techonology, Itami, Japan</span></span></i></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Michael Phan</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">, </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Qualcomm, Raleigh, NC</span></span></i></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-weight: normal;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: 13px;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Joo Sun Choi</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">, </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Samsung Electronics, Hwasung, Korea</span></span></i></span></span></span></b></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: 13px;"><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Bob Payne</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">, </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Texas Instruments, Dallas, TX</span></span></i></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: 13px;"><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Vladimir Stojanovic</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">, </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">MIT, Cambridge, MA</span></span></i></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: 13px;"><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Kees Van Berkel</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">, </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">ST- Ericsson, Eindhoven, The Netherlands</span></span></i></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: 13px;"><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Takayasu Sakurai</span></span></b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">, </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">University of Tokyo, Tokyo, Japan</span></span></i></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"><br />
</span> </span></div><div><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">This Forum brings together 3D-integration technologies (System-in-Package, Through-Silicon-Via, Contactless-Chip-to-Chip-Communication,...), key components (SDRAM, flash, SoC, sensor,...) and 3D applications (imagers, smart phones, solid-state disk drives,...).</span></div><div><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"><br />
</span> </div><div><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Key issues addressed by the panel experts will include:</span></div><div><ul><li><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">3D-integration standards</span></li>
<li><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">3D-integration technologies: SiP, Chip-Scale Packages, Bit-Cost-Scalable 3D cell stacking, TSV, contactless interfaces,...</span></li>
<li><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Power issues, mechanical issues, temperature distribution</span></li>
<li><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Product benefits and yields</span></li>
</ul></div><div><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">And, finally, the panel will provide an answer to the question: When will 3D be ready for show time?</span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"><br />
</span> </span></div><div><b><u><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Forum Agenda:</span></span></u></b><br />
<b><u><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"><br />
</span></span></u></b></div><div><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> <u>Time</u> <u>Topic</u></span></span></b></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="color: #cccccc;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></span></b></span><span class="Apple-style-span" style="color: #cccccc;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">8:00 </span></span><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="color: #cccccc;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span class="Apple-style-span" style="font-weight: normal;"><span class="Apple-style-span" style="color: #cccccc;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Breakfast</span></span></span></span></b></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></b></span><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">8:20 </span><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: medium; font-weight: normal;"><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Introduction</span></span></b></span></span></b></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: medium; font-weight: normal;"><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Pascal Urard, STMicroelectronics, Crolles, France</span></span></i></span></span></b></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></b></span><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">8:30 </span><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: medium; font-weight: normal;"><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">3D TSVs - Ready for Design!</span></span></b></span></span></b></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Pol Marchal, IMEC, Leuven, Belgium</span></span></i></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></b></span><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">9:15 </span><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: medium; font-weight: normal;"><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">3D for Wireless Mobile Multimedia Applications - Opportunities and Challenges</span></span></b></span></span></b></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: medium; font-weight: normal;"><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Georg Kimmich, ST-Ericsson, Grenoble, France</span></span></i></span></span></b></span></span><br />
<span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"></span></div><div><span style="font-size: medium;"><b><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></b><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">10:00 </span><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-weight: normal;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Break</span></span></span></b></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></b></span><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">10:15 </span><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: medium; font-weight: normal;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Chip-Scale Camera Module Using Through-Silicon-Via</span></span></b></span></span></b></span></span><br />
<span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: medium; font-weight: normal;"><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Jean-Luc Jaffard, STMicroelectronics, Grenoble, France</span></span></i></span></span></b></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></b></span><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">11:00 </span><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="font-size: medium; font-weight: normal;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">2.5D & 3D ICs: Solutions & Challenges</span></span></b></span></span></b></span></span><br />
<span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Ho-Ming Tong, ASE Group, Kaoshiung, Taiwan</span></span></i></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></b></span><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">11:45 </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Contactless Interfaces in 3D-Integration</span></span></b></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Hiroki Ishikuro, Keio University, Yokohama, Japan</span></span></i></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="color: #cccccc;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></span></b></span><span class="Apple-style-span" style="color: #cccccc;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">12:30 Lunch</span></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></b></span><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">1:30 </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Advancements in SiP Integration and Interconnect Technology</span></span></b></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Flynn Carson, STATS ChipPACK, Singapore</span></span></i></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></b></span><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">2:15 </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">TSV Technology and its Application to DRAM</span></span></b></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Uksung Kang, Samsung, Korea</span></span></i></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span><span class="Apple-style-span" style="color: #cccccc;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></span></b></span><span class="Apple-style-span" style="color: #cccccc;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">3.00 Break</span></span></span></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></b></span><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">3:15 </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">3D Flash Memory Technology and Circuit Design</span></span></b></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Yoshihisa Iwata, Toshiba, Yokohama, Japan</span></span></i></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></b></span><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">4:00 </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">3D Integration Challenges in Computing</span></span></b></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span><i><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Samuel Naffziger, AMD, Fort Collins, CO</span></span></i></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></b></span><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">4:10 </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Panel Discussion</span></span></b></div><div><span style="font-size: medium;"><span class="Apple-style-span" style="font-size: medium;"><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;"> </span></span></b></span><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">5:10 </span></span><b><span style="font-size: medium;"><span class="Apple-style-span" style="font-family: 'Helvetica Neue', Arial, Helvetica, sans-serif;">Conclusion</span></span></b></div><br />
<hr ...>Deanshttp://www.blogger.com/profile/05038697381190002337noreply@blogger.com0