This is an especially interesting topic for me, as we're pursuing a solution that demonstrates the performance, high degree of connectivity and integration that's typically associated with TSVs, while maintaining cost and manufacturability that is more consistent with state of the art 3D packaging techniques.
In the "It's a small world" category, the story features commentary from Dr. Bill Bottoms, the presenter at the IEEE CPMT-SCV Meeting - 3D IC Integration: The Next Generation of Electronics back in March of this year.
Of course, the article contains the oft-heard refrain about mobile being the driver for this technology (with which I heartily agree):
So why the drive to push past all these challenges? In short, the mobile market is extremely enticing. In the past, standard cell phone technology called for added functionality, decreased size, extended battery life, and lower cost. "Ultimately, the goal there was to get cell phones into as many people's hands as we possibly could in the industry," said Dave Stepniak, manager of wafer-level packaging at Texas Instruments (TI). "And the industry did a great job there; there's about 4.6 billion people today that use cell phones, and that's a good percentage of the world population."
But the market gets even more lucrative for chipmakers heading into the market for smart phones and other mobile devices with further increasing functionality. The silicon content in a smart phone could total more than $70, Stepniak said, compared with just a few dollars for a standard cell phone. "So it's a good market space for the semiconductor; it's very healthy for us, and it's a growing market," he said, adding that the smart phone market is expected to grow from approximately 250 million units to approximately 450 million units over the next couple years.
Besides increased memory capacity and bandwidth, the new consumer technologies require lower operating voltages to increase battery life, higher frequencies, and increased I/Os. In terms of die size, not only are x and y important, but also height. Devices are getting thinner and thinner, creating additional challenges with warpage on the package side.
"What we see as we move forward relative to the increasing frequencies is that the wire bond is running out of steam," Stepniak noted. "As you go above 1 GHz, you start to go to flip chip because of the parasitics that start to play within that package." Flip chip, however, is beginning to push the limits of I/O density, prompting designers to explore new packaging possibilities.
The discussion includes coverage of die embedding and fine pitch copper pillars (pitches to 50 µm are on their, courtesy of TI). It's well worth a read, and please keep watching us as we're hoping to be able to reveal more details regarding our work very soon.
Happy Stacking!
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