Elpida Prepping for 3-D Commercialization

Semiconductor International has a very informative story regarding 3-D directions at Elpida Memory, Inc.

Applied Materials Announces New Equipment for 3-D

Applied Materials recently put out a press release to announce some very interesting new equipment for 3-D fabrication.  The Applied Producer® InVia™ dielectric deposition system uses CVD to deposit the oxide liner for TSVs.  The company claims that their new equipment:

SanDisk 32GB microSDHC - Stack of 8 4GB die

Mostly, I'm sharing this story because of the cool photo that Wired's GadgetLab included.  The basic news is that SanDisk has announced a 32 GByte microSDHC card.  They used a 32 nm process (cool symmetry — 32 billion bytes and 32 billionths of a meter) and arranged the die in an 8 high stack of 4 GB die.  Apparently the suggested retail price is around US$200.

IMAPS Conference - Great Stuff!

The International Microelectronics and Packaging Society (IMAPS) recently wrapped up their 6th International Conference and Exhibition on Device Packaging.  For those of us that couldn't swing a week in Scottsdale, we can thank Dr. Phil Garrou, the event's General Chair, and well known 3D technology expert, for posting a great synopsis.  Some of the key points include:

Quantum Film - CMOS Image Sensor Killer?

This is kind of off topic, but since image sensors are among the first commercial success stories for vertical integration, I thought that it was worth noting.  InVisage Technologies, Inc. has announced the development of a "quantum film" that represents a dramatic improvement over current technologies.  According to the story in EETimes, the InVisage process involves suspending lead-sulfide nanoparticles in a polymer matrix.  Here's the pertinent bit from the story:

Novellus & IBM Form Cu TSV Joint Dev Program

This press release from Novellus flashed across my screen today.  Apparently they have set up a joint effort with IBM to commercialize a Cu TSV process using:

IBM Chilling Chip Stacks with Fluid in Microchannels

EETimes has a very interesting story about work at IBM, along with École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH).  They're using fluids (including, perhaps, water) passing through 50 µm diameter microchannels to cool stacked die.

IMEC Using Synopsys TCAD Simulation Tools

After my recent blurb regarding the readiness of design tools to tackle 3D integration, I feel like I need to present at least some of the other side.

Tier Logic Uncloaks – It’s a 3D FPGA Company!

Just as I was getting ready to head over to the IEEE CPMT-SCV 3D IC Integration meeting last night, this fascinating story popped up.  Tier Logic, a Santa Clara 3D FPGA venture has finally dropped their cloak of invisibility to reveal another 3D FPGA company.

IEEE CPMT-SCV Meeting Report - 3D IC Integration: The Next Generation of Electronics (Updated)

The IEEE Components, Packaging and Manufacturing Technology Society, Santa Clara Valley Chapter put together a great program last night:  "3D IC Integration: The Next Generation of Electronics."  The speaker, Dr. W. R. Bottoms, did a wonderful job of illuminating the current state of the industry.  He clearly shares the excitement that we've been blogging about.  I even managed to pick up some interesting tidbits by paying attention to the conversations at the meeting.

Dr. Garrou on SEMI's Industry Strategy Symposium 2010

One of the benefits of following sources like Perspectives From the Leading Edge is that I get a peek into events that wouldn't allow a simple engineer like me through the venue doors.

ALLVIA Integrates Embedded Capacitors into Silicon Interposers

The smart folks over at ALLVIA have integrated passive components directly into the silicon interposer that resides between the die and the substrate.