EETimes: Momentum builds for 3-D chips

The wise folks over at EETimes have a nice piece identifying the "rise" (get it?) of die stacking.

I agree completely with this bit:

…There are fears that IC scaling is becoming too costly for most chip makers-or will end in the distant future.

So instead of scaling, there is another concept on the table: stack and connect devices in a 3-D configuration…

My only slight quibble is with the exclusive focus on TSVs.  While Through Silicon Vias are clearly the mainstream solution, they still present numerous issues with alignment, die area, thermal expansion and capacitance.  I'm still looking for a better way, perhaps something more along the lines of the work going on over at MonolithIC 3D.  Anyway, it's nice to see our space getting some love from EETimes.

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