The demand for higher densities, smaller form factors, and greater functionality, and the quest for developing post-CMOS technologies is spurring ongoing research in a wide variety of wafer-scale integration techniques. This program brings together experts from academia and the semiconductor industry to examine the state of research into 3D interconnect, unit-process development and integration, and production qualification.The list of speakers is particularly impressive:
My point in highlighting a sold out meeting is to suggest that this topic is intensely interesting to a broad range of academic and industry professionals. Clearly, the excitement around progress in this area is building (hype notwithstanding).
- Matt Nowak, Qualcomm. Taming Cost and Design Challenges for High Density Through Silicon Stacking (TSS).
- Xiaopeng Xu, Synopsys. Modeling Thermo-Mechanical Stress Impact on Performance and Reliability of 3D Integration Structures.
- Sesh_Ramaswami, Applied Materials. Journey Toward Process Convergence in TSV Technology
- Zvi Or-Bach, NuPGA. 3D FPGA - The Path to ASIC Density, Power, and Performance.
- Deepak C. Sekar, SanDisk. A 3D-IC Technology with Integrated Microfluidic Cooling.
- Arif Rahman, Xilinx, Inc. Technology Requirements and Standardization for 3-D SiP.
- Tom Ritzdorf, Semitool. Advances in Copper Fill for 3D Interconnect Applications.
- William Chen, ASE Group. 3D and More: A Renaissance in the Making.
- Raj Pendse, STATS ChipPAC 3D Integration: The Evolution of Device Architecture, Packaging, and Manufacturing Infrastructure
- C. Raman Kothandaraman, IBM Through Silicon Via (TSV) for 3D integration
I just wish that I'd been able to participate. I'll certainly be there in the future.
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