2010/02/02

NuPGA Leverages 3D Stacks to Revolutionize Programmable Logic

EETimes had a great article covering the exciting developments at NuPGA (Their site is currently "Under Construction" — Hopefully more will come, soon).

Those who were in the reconfigurable logic wars a few years ago might recognize the company's founder, Zvi Or-Bach, from his time at eASIC and Chip Express.

Mr. Or-Bach spoke passionately about his new venture at the recent IEEE SCV EDS Symposium: 3D Interconnect - Shaping Future Technology.  He makes the case that NuPGA is will shake up the configurable logic space through the innovative use of stacking to place the large programming transistors on a separate die.  With this architecture, the programming xtors don't add to the X/Y area of his anti-fuse based arrays.  As reported in the story:

NuPGA's 3-D construction technique first fabricates a foundation wafer containing the high-voltage programming transistors interconnected by high-temperature tungsten metalization and capped with an oxide layer. Then a second blank silicon wafer is capped with oxide, flipped and bonded to the foundation wafer oxide-to-oxide. The top wafer is then "smart cut"—a method borrowed producers of silicon-on-insulator wafers—to form a silicon surface for the rest of the FPGA. Normal wafer processing steps can then fabricate the gate array which is topped by the anti-fuse interconnection layer.

This story is interesting on a couple of levels.  First, I'm happy to see another near term application for the technology.  It's also gratifying to see that someone with Mr. Or-Bach's credentials recognizes the value of vertical integration.  I hope that NuPGA breaks the trend for reconfigurable computing startups  and finds some real success.


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