IEEE CPMT-SCV Meeting Report - 3D IC Integration: The Next Generation of Electronics (Updated)

The IEEE Components, Packaging and Manufacturing Technology Society, Santa Clara Valley Chapter put together a great program last night:  "3D IC Integration: The Next Generation of Electronics."  The speaker, Dr. W. R. Bottoms, did a wonderful job of illuminating the current state of the industry.  He clearly shares the excitement that we've been blogging about.  I even managed to pick up some interesting tidbits by paying attention to the conversations at the meeting.

Dr. Garrou on SEMI's Industry Strategy Symposium 2010

One of the benefits of following sources like Perspectives From the Leading Edge is that I get a peek into events that wouldn't allow a simple engineer like me through the venue doors.

Exciting 3D IC Integration Event Coming Up!

The IEEE Components, Packaging and Manufacturing Technology Society, Santa Clara Valley Chapter is putting together what promises to be an extremely interesting program titled, "3D IC Integration: The Next Generation of Electronics."  The fun will commence at 6:00 PM on Wednesday, March 10, 2010, in Santa Clara.

End of CMOS Scaling? Ho-Hum - Wrong Question!

The International Solid-State Circuits Conference (ISSCC) is currently underway in San Francisco.  As has been the case for as long as I can remember, the attendees are apparently (I couldn't swing attending the conference) discussing the end of the world as we know it.  Variously referred to as the end of silicon scaling, the end of CMOS viability and the end of Moore's law, the premise is always the same.  At xx node, silicon just won't work anymore.  Generally I just let this conversation flow over me, but one story in EETimes caught my eye.