IBM Chilling Chip Stacks with Fluid in Microchannels

EETimes has a very interesting story about work at IBM, along with École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH).  They're using fluids (including, perhaps, water) passing through 50 µm diameter microchannels to cool stacked die.

IEEE CPMT-SCV Meeting Report - 3D IC Integration: The Next Generation of Electronics (Updated)

The IEEE Components, Packaging and Manufacturing Technology Society, Santa Clara Valley Chapter put together a great program last night:  "3D IC Integration: The Next Generation of Electronics."  The speaker, Dr. W. R. Bottoms, did a wonderful job of illuminating the current state of the industry.  He clearly shares the excitement that we've been blogging about.  I even managed to pick up some interesting tidbits by paying attention to the conversations at the meeting.

Dr. Garrou on SEMI's Industry Strategy Symposium 2010

One of the benefits of following sources like Perspectives From the Leading Edge is that I get a peek into events that wouldn't allow a simple engineer like me through the venue doors.

ALLVIA Integrates Embedded Capacitors into Silicon Interposers

The smart folks over at ALLVIA have integrated passive components directly into the silicon interposer that resides between the die and the substrate.

Progress on Driving Down the Cost of TSVs

The cover story in Semiconductor International's February 2010 issue is Driving Down the Cost of TSVs.  The story provides good insight into the progress towards reducing the cost of the entire TSV process flow.

Semi-Therm Course: Cooling Challenges in 3D Packaging

For those, like me, that don't cast our info nets nearly wide enough, this event might have escaped our attention.  That is unfortunate.  The 26th Annual Thermal Measurement, Modeling and Management Symposium is being held next week in Santa Clara.  One course, "Cooling Challenges in 3D Packaging" is of particular interest to those who follow this humble blog.  The short course will be presented by Dereje Agonafer, Ph.D.  Dr. Agonafer is a Professor and Director, Elec, MEMS & Nanoelectronics Systems Packaging Center at the University of Texas at Arlington (Faculty profile).

End of CMOS Scaling? Ho-Hum - Wrong Question!

The International Solid-State Circuits Conference (ISSCC) is currently underway in San Francisco.  As has been the case for as long as I can remember, the attendees are apparently (I couldn't swing attending the conference) discussing the end of the world as we know it.  Variously referred to as the end of silicon scaling, the end of CMOS viability and the end of Moore's law, the premise is always the same.  At xx node, silicon just won't work anymore.  Generally I just let this conversation flow over me, but one story in EETimes caught my eye.

NuPGA Leverages 3D Stacks to Revolutionize Programmable Logic

EETimes had a great article covering the exciting developments at NuPGA (Their site is currently "Under Construction" — Hopefully more will come, soon).

2010 IEEE SCV-EDS/Applied Materials Technical Symposium - Sold Out

Unfortunately, I've been a bit lax in keeping up with my IEEE event announcements, so I didn't notice this symposium until a colleague brought it to my attention.  When I tried to register, I discovered, to my dismay, that the meeting was already "full."  Sadness…  It looks like it will be extremely interesting:

IC Insights Predicts Delays for TSVs

And just as we're getting started, comes this somewhat glum commentary from IC Insights. According to the story from CommsDesign: