Is it Packaging, or is it Fab?

There's an interesting story up on EDN, titled "Wafer-level packaging pushes past new mobile demands."  The gist of the discussion seems to be exploring where packaging ends and 3-D IC fabrication begins.

Farewell Tier Logic - We hardly knew you

I'm quite disheartened by the report that Tier Logic has gone the way of so many other promising FPGA startups.

TSMC Vaporware: 3-D "Ecosystem"

EETimes reports that TSMC is:

"… putting the pieces in place to enable 3-D designs based on silicon interposers and through silicon vias (TSVs)."

SanDisk 32GB microSDHC - Stack of 8 4GB die

Mostly, I'm sharing this story because of the cool photo that Wired's GadgetLab included.  The basic news is that SanDisk has announced a 32 GByte microSDHC card.  They used a 32 nm process (cool symmetry — 32 billion bytes and 32 billionths of a meter) and arranged the die in an 8 high stack of 4 GB die.  Apparently the suggested retail price is around US$200.

IMAPS Conference - Great Stuff!

The International Microelectronics and Packaging Society (IMAPS) recently wrapped up their 6th International Conference and Exhibition on Device Packaging.  For those of us that couldn't swing a week in Scottsdale, we can thank Dr. Phil Garrou, the event's General Chair, and well known 3D technology expert, for posting a great synopsis.  Some of the key points include:

Quantum Film - CMOS Image Sensor Killer?

This is kind of off topic, but since image sensors are among the first commercial success stories for vertical integration, I thought that it was worth noting.  InVisage Technologies, Inc. has announced the development of a "quantum film" that represents a dramatic improvement over current technologies.  According to the story in EETimes, the InVisage process involves suspending lead-sulfide nanoparticles in a polymer matrix.  Here's the pertinent bit from the story:

IMEC Using Synopsys TCAD Simulation Tools

After my recent blurb regarding the readiness of design tools to tackle 3D integration, I feel like I need to present at least some of the other side.

Tier Logic Uncloaks – It’s a 3D FPGA Company!

Just as I was getting ready to head over to the IEEE CPMT-SCV 3D IC Integration meeting last night, this fascinating story popped up.  Tier Logic, a Santa Clara 3D FPGA venture has finally dropped their cloak of invisibility to reveal another 3D FPGA company.

IEEE CPMT-SCV Meeting Report - 3D IC Integration: The Next Generation of Electronics (Updated)

The IEEE Components, Packaging and Manufacturing Technology Society, Santa Clara Valley Chapter put together a great program last night:  "3D IC Integration: The Next Generation of Electronics."  The speaker, Dr. W. R. Bottoms, did a wonderful job of illuminating the current state of the industry.  He clearly shares the excitement that we've been blogging about.  I even managed to pick up some interesting tidbits by paying attention to the conversations at the meeting.

Dr. Garrou on SEMI's Industry Strategy Symposium 2010

One of the benefits of following sources like Perspectives From the Leading Edge is that I get a peek into events that wouldn't allow a simple engineer like me through the venue doors.

ALLVIA Integrates Embedded Capacitors into Silicon Interposers

The smart folks over at ALLVIA have integrated passive components directly into the silicon interposer that resides between the die and the substrate.

Great Blog: Perspectives From the Leading Edge

I recently came across another great blog, "Perspectives From the Leading Edge," that focuses on vertical integration technology.

Progress on Driving Down the Cost of TSVs

The cover story in Semiconductor International's February 2010 issue is Driving Down the Cost of TSVs.  The story provides good insight into the progress towards reducing the cost of the entire TSV process flow.

IEEE: Design Challenges Loom for 3-D Chips

A very good overview of the current state of TSV technology came out today on the IEEE Spectrum site.  The whole piece is well worth a read, and I strongly encourage everyone with an interest in the subject to check it out.  The first illustration is priceless

ALLVIA Presentation: Through Silicon Vias - Design & Reliability

I came across this excellent slide deck titled Through Silicon Vias (TSV):  Design and Reliability (PDF) from our friends at ALLVIA, the TSV foundry specialists.

Exciting 3D IC Integration Event Coming Up!

The IEEE Components, Packaging and Manufacturing Technology Society, Santa Clara Valley Chapter is putting together what promises to be an extremely interesting program titled, "3D IC Integration: The Next Generation of Electronics."  The fun will commence at 6:00 PM on Wednesday, March 10, 2010, in Santa Clara.

Semi-Therm Course: Cooling Challenges in 3D Packaging

For those, like me, that don't cast our info nets nearly wide enough, this event might have escaped our attention.  That is unfortunate.  The 26th Annual Thermal Measurement, Modeling and Management Symposium is being held next week in Santa Clara.  One course, "Cooling Challenges in 3D Packaging" is of particular interest to those who follow this humble blog.  The short course will be presented by Dereje Agonafer, Ph.D.  Dr. Agonafer is a Professor and Director, Elec, MEMS & Nanoelectronics Systems Packaging Center at the University of Texas at Arlington (Faculty profile).

ISSCC Forum: Silicon 3D-Integration Technology and Systems

I'm really mad at myself for not heading up to the ISSCC this year.  The conference featured a full day forum on 3D Integration.  Although I'm sorry that I missed it, I'm thrilled by the attention, as it clearly demonstrates just how important this technology is becoming.  I was particularly gratified to see a good mix of industry and academic interests involved in the 3D forum.