Showing posts with label thru-silicon-vias. Show all posts
Showing posts with label thru-silicon-vias. Show all posts
2010/03/30
Elpida Prepping for 3-D Commercialization
Semiconductor International has a very informative story regarding 3-D directions at Elpida Memory, Inc.
Labels:
3D devices,
3D interconnect,
Elpida,
thru-silicon-vias,
TSV
Applied Materials Announces New Equipment for 3-D
Applied Materials recently put out a press release to announce some very interesting new equipment for 3-D fabrication. The Applied Producer® InVia™ dielectric deposition system uses CVD to deposit the oxide liner for TSVs. The company claims that their new equipment:
Labels:
3D interconnect,
Applied Materials,
thru-silicon-vias,
TSV
2010/03/17
Novellus & IBM Form Cu TSV Joint Dev Program
This press release from Novellus flashed across my screen today. Apparently they have set up a joint effort with IBM to commercialize a Cu TSV process using:
Labels:
3D devices,
3D interconnect,
Cu,
IBM,
Novellus,
Tezzaron,
thru-silicon-vias,
TSV
2010/03/11
IMEC Using Synopsys TCAD Simulation Tools
After my recent blurb regarding the readiness of design tools to tackle 3D integration, I feel like I need to present at least some of the other side.
Labels:
3D devices,
3D integration,
3D interconnect,
IMEC,
Synopsys,
thru-silicon-vias,
TSV
2010/02/19
Progress on Driving Down the Cost of TSVs
The cover story in Semiconductor International's February 2010 issue is Driving Down the Cost of TSVs. The story provides good insight into the progress towards reducing the cost of the entire TSV process flow.
Labels:
3D integration,
3D interconnect,
stacked die,
thru-silicon-vias,
TSV
2010/02/17
IEEE: Design Challenges Loom for 3-D Chips
A very good overview of the current state of TSV technology came out today on the IEEE Spectrum site. The whole piece is well worth a read, and I strongly encourage everyone with an interest in the subject to check it out. The first illustration is priceless
Labels:
3D devices,
3D integration,
3D interconnect,
thru-silicon-vias,
TSV
2010/02/12
ALLVIA Presentation: Through Silicon Vias - Design & Reliability
I came across this excellent slide deck titled Through Silicon Vias (TSV): Design and Reliability (PDF) from our friends at ALLVIA, the TSV foundry specialists.
2010/02/11
ISSCC Forum: Silicon 3D-Integration Technology and Systems
I'm really mad at myself for not heading up to the ISSCC this year. The conference featured a full day forum on 3D Integration. Although I'm sorry that I missed it, I'm thrilled by the attention, as it clearly demonstrates just how important this technology is becoming. I was particularly gratified to see a good mix of industry and academic interests involved in the 3D forum.
Labels:
3D devices,
3D integration,
ISSCC,
thru-silicon-vias,
TSV
2010/02/02
NuPGA Leverages 3D Stacks to Revolutionize Programmable Logic
EETimes had a great article covering the exciting developments at NuPGA (Their site is currently "Under Construction" — Hopefully more will come, soon).
Labels:
3D devices,
3D interconnect,
FPGA,
stacked die,
thru-silicon-vias,
TSV
2010/01/25
IC Insights Predicts Delays for TSVs
And just as we're getting started, comes this somewhat glum commentary from IC Insights. According to the story from CommsDesign:
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