Is it Packaging, or is it Fab?

There's an interesting story up on EDN, titled "Wafer-level packaging pushes past new mobile demands."  The gist of the discussion seems to be exploring where packaging ends and 3-D IC fabrication begins.

Elpida Prepping for 3-D Commercialization

Semiconductor International has a very informative story regarding 3-D directions at Elpida Memory, Inc.

SanDisk 32GB microSDHC - Stack of 8 4GB die

Mostly, I'm sharing this story because of the cool photo that Wired's GadgetLab included.  The basic news is that SanDisk has announced a 32 GByte microSDHC card.  They used a 32 nm process (cool symmetry — 32 billion bytes and 32 billionths of a meter) and arranged the die in an 8 high stack of 4 GB die.  Apparently the suggested retail price is around US$200.

IMAPS Conference - Great Stuff!

The International Microelectronics and Packaging Society (IMAPS) recently wrapped up their 6th International Conference and Exhibition on Device Packaging.  For those of us that couldn't swing a week in Scottsdale, we can thank Dr. Phil Garrou, the event's General Chair, and well known 3D technology expert, for posting a great synopsis.  Some of the key points include:

Novellus & IBM Form Cu TSV Joint Dev Program

This press release from Novellus flashed across my screen today.  Apparently they have set up a joint effort with IBM to commercialize a Cu TSV process using:

IBM Chilling Chip Stacks with Fluid in Microchannels

EETimes has a very interesting story about work at IBM, along with École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH).  They're using fluids (including, perhaps, water) passing through 50 µm diameter microchannels to cool stacked die.

IMEC Using Synopsys TCAD Simulation Tools

After my recent blurb regarding the readiness of design tools to tackle 3D integration, I feel like I need to present at least some of the other side.

Tier Logic Uncloaks – It’s a 3D FPGA Company!

Just as I was getting ready to head over to the IEEE CPMT-SCV 3D IC Integration meeting last night, this fascinating story popped up.  Tier Logic, a Santa Clara 3D FPGA venture has finally dropped their cloak of invisibility to reveal another 3D FPGA company.

ALLVIA Integrates Embedded Capacitors into Silicon Interposers

The smart folks over at ALLVIA have integrated passive components directly into the silicon interposer that resides between the die and the substrate.

Great Blog: Perspectives From the Leading Edge

I recently came across another great blog, "Perspectives From the Leading Edge," that focuses on vertical integration technology.

IEEE: Design Challenges Loom for 3-D Chips

A very good overview of the current state of TSV technology came out today on the IEEE Spectrum site.  The whole piece is well worth a read, and I strongly encourage everyone with an interest in the subject to check it out.  The first illustration is priceless

ISSCC Forum: Silicon 3D-Integration Technology and Systems

I'm really mad at myself for not heading up to the ISSCC this year.  The conference featured a full day forum on 3D Integration.  Although I'm sorry that I missed it, I'm thrilled by the attention, as it clearly demonstrates just how important this technology is becoming.  I was particularly gratified to see a good mix of industry and academic interests involved in the 3D forum.

IEEE SCV EDS Symposium: 3D Interconnect - Shaping Future Technology (Updated)

Thanks to a much appreciated intervention by Dr. Prasad Chaparala, the event chairman, I was able to attend the IEEE SCV EDS Symposium: 3D Interconnect - Shaping Future Technology after all.  It was fantastic!  The information and insight were priceless.  I've started preparing a series of posts covering the event, of which this will be the first.

NuPGA Leverages 3D Stacks to Revolutionize Programmable Logic

EETimes had a great article covering the exciting developments at NuPGA (Their site is currently "Under Construction" — Hopefully more will come, soon).

2010 IEEE SCV-EDS/Applied Materials Technical Symposium - Sold Out

Unfortunately, I've been a bit lax in keeping up with my IEEE event announcements, so I didn't notice this symposium until a colleague brought it to my attention.  When I tried to register, I discovered, to my dismay, that the meeting was already "full."  Sadness…  It looks like it will be extremely interesting:

IC Insights Predicts Delays for TSVs

And just as we're getting started, comes this somewhat glum commentary from IC Insights. According to the story from CommsDesign: