Dr. Garrou on SEMI's Industry Strategy Symposium 2010

One of the benefits of following sources like Perspectives From the Leading Edge is that I get a peek into events that wouldn't allow a simple engineer like me through the venue doors.

Philip Garrou just posted about SEMI's recent Industry Strategy Symposium (ISS 2010).

You really should just go read Dr. Garrou's post, but there were a couple of bits that particularly stood out for me.

First, Dr. Handel H. Jones, who once was kind enough to do some consulting for one of my ventures when we were way too poor to pay him, and thus to whom I am forever in debt, suggested that:

"…the cost per gate actually goes up at 22 nm"

That's right, it goes up.  This puts even more wood behind the arrow of achieving higher functionality through vertical integration, rather than 2-D device scaling, as does the following.

Dr. Garrou cites work from both NC State and Toshiba to reach the following conclusion:

"… it is clear from all published results so far that 3D allows you to achieve improved performance at a higher node which translates into lower cost if and when 3D reaches the necessary cost points."

Seeing is believing so:

Shifting away from ISS 2010…, 4D Chips has been involved in a series of discussions recently that strongly suggest that 2010 will be the year when a whole raft of commercial products leveraging 3-D chips will hit the market.  Unfortunately, I'm under NDA regarding the specifics, but I'm more convinced than ever that this is the year of vertical integration.

---