Tier Logic Uncloaks – It’s a 3D FPGA Company!

Just as I was getting ready to head over to the IEEE CPMT-SCV 3D IC Integration meeting last night, this fascinating story popped up.  Tier Logic, a Santa Clara 3D FPGA venture has finally dropped their cloak of invisibility to reveal another 3D FPGA company.

Because I'm more than a little lazy (and I don't get paid to blog), permit me to quote from Ron Wilson's excellent post over on EDN:

TierLogic's big idea is elegant and audacious: increase the density of FPGAs by moving all the configuration memory—not the data memory or the look-up-table (LUT) memory, but the RAM cells that control the interconnect muxes—out of the silicon.  Removing these memory bits by itself can cut die area—at least the die area occupied by logic fabric—more than in half, according to the company's vice president of sales and marketing, Paul Hollingworth.  TierLogic employs this advantage to use a mature 90nm process node and still deliver a smaller die area than a conventional SRAM FPGA would require, making it possible to offer the FPGAs at about half the cost of equivalent conventional parts.

But those SRAM cells have to go somewhere.  That's where TierLogic's foundry partner Toshiba comes into the picture.  Toshiba has developed a unique back-end-of-line process that puts a layer of amorphous-silicon thin-film transistors (TFTs) on top of the interconnect stack.  The proprietary process uses virtually none of the wafer's thermal budget, so it's compatible with advanced CMOS.  Yet at 180nm dimensions Toshiba can produce sufficiently fast and dense TFT SRAM cells to accommodate all the configuration memory required for the FPGA below.  And since the configuration SRAM just sits there providing steering bits to the muxes—no user delay paths pass through the configuration memory—the slower, more stable TFT SRAM has no impact on user timing, except for the significant benefit of allowing the active die area be much smaller.

Illustration of Tier Logic Technology

Mr. Wilson goes on to observe that this approach not only provides much better density (as much as 3x standard FPGAs), but that it provides a very quick, and accurate, path to creating mask-programmed devices.  If you're interested in the subject, you should check out the original post.  There's also a story in EETimes.

Using TFT's for the configuration memory is a fascinating approach.  4D Chips has looked at similar architectures, where the configuration memory was actually in a second die (conceptually, we're thinking more along the lines of the work going on over at NuPGA), but the Tier Logic architecture is certainly intriguing.

By the way, as Mr. Wilson ably points out, Both NuPGA and Tier Logic are developing FPGAs that leverage vertical integration.  The third dimension in the recent announcement from Tabula is time, not stacked die.  I was going to do a post about Tabula, but it doesn't ever seem to bubble up on the priority list.  Just in case it never does, EETimes has an excellent article describing the company and the technology.

This is certainly an exciting time for 3D.

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