End of CMOS Scaling? Ho-Hum - Wrong Question!

The International Solid-State Circuits Conference (ISSCC) is currently underway in San Francisco.  As has been the case for as long as I can remember, the attendees are apparently (I couldn't swing attending the conference) discussing the end of the world as we know it.  Variously referred to as the end of silicon scaling, the end of CMOS viability and the end of Moore's law, the premise is always the same.  At xx node, silicon just won't work anymore.  Generally I just let this conversation flow over me, but one story in EETimes caught my eye.


The story quotes James Meindl, a Plenary Session presenter as saying,

"We will continue to scale vigorously for the next 15 years.  Beyond silicon microchip technology, revolutionary developments in nanoelectronics, perhaps centering on graphene, may evolve."

The reporter continues to summarize the remarks, writing that:

"For processors, silicon could scale to the 7.9-nm node, which is slated for 2024. Before or after that, graphene could enable future terascale computing"

While this may very well be accurate (I love the potential that graphene presents, and I've paid close attention to the recent reports — a handful are here, here and here), the best case is that many tens of billions of dollars will be spent pursuing ever smaller features in silicon for the next decade and a half.  The real question should be, "Why?"

While smart engineers know when to step out of the path of the onrushing locomotive, dumb ones, like me, are always asking whether there might be another option.  Of course, I have a particular point of view on this, but I feel strongly that vertical integration provides a more direct path to providing more functionality on shrinking system boards, while consuming less power and readily supporting architectures that require extreme interconnect bandwidth.  I'm all for pushing silicon as far as we can.  I'm just saying that we shouldn't forget to look up as well as in.

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