IEEE: Design Challenges Loom for 3-D Chips

A very good overview of the current state of TSV technology came out today on the IEEE Spectrum site.  The whole piece is well worth a read, and I strongly encourage everyone with an interest in the subject to check it out.  The first illustration is priceless

Although much of the article rehashes the "Four Horsemen" of vertical integration:  Manufacturing Cost, Test, Thermal Management and Design — it's still a valuable snapshot of developments in the technology.  I especially appreciated the discussion of whether 3D assembly belongs with the foundry, the packaging house, or some (as yet) unnamed third participant.

For me, the money quote is from Pol Marchal, a principal scientist of 3-D integration at IMEC (Interuniversity Microelectronics Centre):

"the industry pull for this technology is big.  TSVs are expected to widely populate chips by 2012 or 2013"

Clearly, now is the time to start exploring this technology and working with organizations like 4D Chips to start preparing for the coming tidal wave of demand.

In the meantime, here's a very cool picture of TSV's from IMEC:



I just noticed that this story was the top piece on the IEEE Spectrum site today.  I hope that there is some sort of statement about the importance of vertical integration in that honored placement.

For those that were wondering, I have no idea why the reporter insists on writing "IMEC" as "Imec."

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