There's so much exciting information to share that I hardly know where to begin. I want to jump right into all of the details. However, in the interest of doing justice to the event, I'll limit this post to listing some of my key takeaways. Future posts will do a deeper dive on the main points.
Some of the highlights for me included:
- Vertical Integration is no longer just a science project — It's real world technology that is currently deployed in shipping products. CMOS image sensors in CE products were cited as a current application of stacked die modules using through silicon via (TSV) technology. I don't have the exact figures in my notes, but something like 40% of the die used in the current generation of smart phones are stacked.
- Several speakers mentioned the "Four Horsemen" of vertical integration: Manufacturing Cost, Test, Thermal Management and Design. These were particularly exciting to me, because the network of partners we're assembling at 4D Chips provides solutions in each of these challenge areas.
- Given the higher costs and increased supply chain complexity, some might wonder why we're pursuing vertical integration. As we mention frequently on our site, the primary motivations center around achieving more functionality, better performance and reduced power consumption, within ever tightening constraints for physical device size and mobility. In particular, speakers emphasized the benefits that can be achieved in terms of minimizing interconnect length, increasing bandwidth between functional blocks, minimizing the need for off chip drivers / ESD protection and supporting heterogeneous integration.
- Sophisticated tools must be deployed early in project planning to ensure proper partitioning and block placement. One speaker, quite accurately, referred to this early process as "pathfinding" &mdash in the sense that designers must explore all dimensions of the design space to ensure satisfactory performance, thermal management and manufacturability.
- As I suggested above, vertical integration results in a more complex supply chain, and requires a very high degree of cooperation throughout the foundry/test/packaging processes.
- Thankfully, there is a book. The Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits runs to nearly 800 pages. This book certainly has the weight to be the definitive work on vertical integration. Unfortunately, the extremely high price (US$223.02) and rapid pace of innovation (the book was published Oct-2008) combine to make me just a bit hesitant to send my money off to Amazon.
One of the organizers promised that the slides presented at the event will be on the SVC-EDS site. Unfortunately, I don't think that they've been uploaded as of this post. I keep checking back, and I'll update when they do show up. As of 2010.02.19, the slides still don't seem to have been posted. However, Semiconductor International wrote a really nice summary of the event that includes many of the illustrations.
Many thanks to Dr. Chaparala, the SVC-EDS team and the staff from Applied Materials. They put on a fantastic symposium, and I'm very grateful for the opportunity to learn so much in such a short time.
As with all such things, making concrete predictions is challenging, but several speakers (and attendees) seemed to share my confidence that we're at an inflection point for vertical integration and that we'll see rapid commercial adoption of the technologies over the next couple of years.
Post script:
Someone recently asked about the acronyms in the event title. IEEE is, of course, the Institute of Electrical and Electronics Engineers. SCV EDS is the Santa Clara Valley Electron Devices Society of the IEEE.
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